-- This is the netlist generated by VHDL Write -- Following changes have been made by hand: -- o port list needs to be small letters (not capital!!), use ctrl-x-l -- o attribute statement has been commented out -- o inline configurations have been commented out -- o entity must be called "top" instead of "fpga_moduletester" -- o architecture must be called "rtl" instead of "structure" -- o rename the instances for the global set/reset as follows -- rstn : IBTPU -- gsr0 : GSR -- o replace the net name GSR0000 by GSR ------------------------------------------------------------ -- LIBRARY STATEMENT LIBRARY ieee; -- PACKAGE STATEMENT USE ieee.std_logic_1164.ALL; entity top is -- GENERIC LIST -- PORT LIST port( board_addr : in std_logic_vector(7 downto 0); input_clk : in std_logic; laddr : in std_logic_vector(31 downto 1); outfifo_efb : in std_logic; outfifo_ffb : in std_logic; rsfifo_data : in std_logic_vector(17 downto 0); rsfifo_efb : in std_logic; rsfifo_ffb : in std_logic; rst : in std_logic; spare_in1 : in std_logic; spare_in2 : in std_logic; svic_cs : in std_logic_vector(5 downto 0); svic_dbe : in std_logic_vector(3 downto 0); svic_lden_n : in std_logic; svic_lds : in std_logic; svic_pren_n : in std_logic; svic_r_w : in std_logic; svic_strobe : in std_logic; svic_swden_n : in std_logic; s_data_in : in std_logic; test : in std_logic; vcomp : in std_logic_vector(3 downto 0); bs_mb0 : out std_logic_vector(2 downto 0); bs_mb1 : out std_logic_vector(2 downto 0); bs_mb2 : out std_logic_vector(2 downto 0); bs_mb3 : out std_logic_vector(2 downto 0); clear_out : out std_logic; clk_data : out std_logic; clk_ld : out std_logic; clk_ld_clk : out std_logic; cs_out : out std_logic_vector(5 downto 0); g_mb0 : out std_logic_vector(1 downto 0); g_mb1 : out std_logic_vector(1 downto 0); g_mb2 : out std_logic_vector(1 downto 0); g_mb3 : out std_logic_vector(1 downto 0); led : out std_logic_vector(8 downto 0); lemo1 : out std_logic; lemo2 : out std_logic; lemo3 : out std_logic; mem_addr_mb0 : out std_logic_vector(17 downto 0); mem_addr_mb1 : out std_logic_vector(17 downto 0); mem_addr_mb2 : out std_logic_vector(17 downto 0); mem_addr_mb3 : out std_logic_vector(17 downto 0); outfifo_data : out std_logic_vector(17 downto 0); outfifo_mrsb : out std_logic; outfifo_oenb : out std_logic; outfifo_renb : out std_logic; outfifo_rtb : out std_logic; outfifo_wenb : out std_logic; rsfifo_mrsb : out std_logic; rsfifo_oenb : out std_logic; rsfifo_renb : out std_logic; rsfifo_rtb : out std_logic; rsfifo_wenb : out std_logic; se3_mb0 : out std_logic_vector(1 downto 0); se3_mb1 : out std_logic_vector(1 downto 0); se3_mb2 : out std_logic_vector(1 downto 0); se3_mb3 : out std_logic_vector(1 downto 0); slow_clk_out : out std_logic; spare_out1 : out std_logic; spare_out2 : out std_logic; svic_lack_n : out std_logic; svic_lirq : out std_logic; svic_region : out std_logic_vector(3 downto 0); sw_mb0 : out std_logic; sw_mb1 : out std_logic; sw_mb2 : out std_logic; sw_mb3 : out std_logic; s_data_out : out std_logic; tc : out std_logic_vector(19 downto 0); vme_xcvr_lds : out std_logic; vme_xcvr_mwb_n : out std_logic; vme_xcvr_strobe_n : out std_logic; ldata : inout std_logic_vector(31 downto 0); mem_datah_mb0 : inout std_logic_vector(8 downto 0); mem_datah_mb1 : inout std_logic_vector(8 downto 0); mem_datah_mb2 : inout std_logic_vector(8 downto 0); mem_datah_mb3 : inout std_logic_vector(8 downto 0); mem_datal_mb0 : inout std_logic_vector(8 downto 0); mem_datal_mb1 : inout std_logic_vector(8 downto 0); mem_datal_mb2 : inout std_logic_vector(8 downto 0); mem_datal_mb3 : inout std_logic_vector(8 downto 0) ); -- attribute original_name : string; end top; -------------------------------------------------------- -- VHDL object: Architecture "structure" (schematic "/home/design/niggli/sim_daq/fpga_moduletester/schematic") of entity "fpga_moduletester" (component interface "/home/design/niggli/sim_daq/fpga_moduletester:fpga_moduletester") -- Generated on: Tue Feb 29 15:32:24 2000 -- Generated by: niggli -- Source from: /home/design/niggli/sim_daq/fpga_moduletester/schematic -- Program: VHDLwrite v8.5_2.2 Wed Jul 31 14:25:07 PDT 1996 -------------------------------------------------------- library hdl; library work; architecture rtl of top is -- TYPE DECLARATIONS -- SIGNAL DECLARATIONS signal N_03613044 : std_logic_vector(31 downto 0); signal N_03614456 : std_logic_vector(31 downto 0); signal local_TC : std_logic_vector(19 downto 0); signal MEM_ADDR_MB0_INT : std_logic_vector(18 downto 0); signal MEM_ADDR_MB1_INT : std_logic_vector(18 downto 0); signal MEM_ADDR_MB2_INT : std_logic_vector(18 downto 0); signal MEM_ADDR_MB3_INT : std_logic_vector(18 downto 0); signal FIFO_OUT_INT : std_logic_vector(17 downto 0); signal local_MEM_ADDR_MB0 : std_logic_vector(17 downto 0); signal local_MEM_ADDR_MB1 : std_logic_vector(17 downto 0); signal local_MEM_ADDR_MB2 : std_logic_vector(17 downto 0); signal local_MEM_ADDR_MB3 : std_logic_vector(17 downto 0); signal N_03613053 : std_logic_vector(17 downto 0); signal N_03613714 : std_logic_vector(17 downto 0); signal N_03613741 : std_logic_vector(17 downto 0); signal local_OUTFIFO_DATA : std_logic_vector(17 downto 0); signal rsfifo_data_int : std_logic_vector(17 downto 0); signal DI_A : std_logic_vector(10 downto 0); signal DI_B : std_logic_vector(10 downto 0); signal QDO_A : std_logic_vector(10 downto 0); signal QDO_B : std_logic_vector(10 downto 0); signal local_LED : std_logic_vector(8 downto 0); signal MEM_DATAH_MB0_I : std_logic_vector(8 downto 0); signal MEM_DATAH_MB0_O : std_logic_vector(8 downto 0); signal MEM_DATAH_MB1_I : std_logic_vector(8 downto 0); signal MEM_DATAH_MB1_O : std_logic_vector(8 downto 0); signal MEM_DATAH_MB2_I : std_logic_vector(8 downto 0); signal MEM_DATAH_MB2_O : std_logic_vector(8 downto 0); signal MEM_DATAH_MB3_I : std_logic_vector(8 downto 0); signal MEM_DATAH_MB3_O : std_logic_vector(8 downto 0); signal MEM_DATAL_MB0_I : std_logic_vector(8 downto 0); signal MEM_DATAL_MB0_O : std_logic_vector(8 downto 0); signal MEM_DATAL_MB1_I : std_logic_vector(8 downto 0); signal MEM_DATAL_MB1_O : std_logic_vector(8 downto 0); signal MEM_DATAL_MB2_I : std_logic_vector(8 downto 0); signal MEM_DATAL_MB2_O : std_logic_vector(8 downto 0); signal MEM_DATAL_MB3_I : std_logic_vector(8 downto 0); signal MEM_DATAL_MB3_O : std_logic_vector(8 downto 0); signal N_03635 : std_logic_vector(8 downto 0); signal N_03612741 : std_logic_vector(7 downto 0); signal N_03614870 : std_logic_vector(7 downto 0); signal N_03615681 : std_logic_vector(7 downto 0); signal local_CS_OUT : std_logic_vector(5 downto 0); signal N_03614249 : std_logic_vector(4 downto 0); signal READ_ADDR_A : std_logic_vector(4 downto 0); signal READ_ADDR_B : std_logic_vector(4 downto 0); signal WRITE_ADDR_A : std_logic_vector(4 downto 0); signal WRITE_ADDR_B : std_logic_vector(4 downto 0); signal MEM0_TRISTATE : std_logic_vector(3 downto 0); signal MEM1_TRISTATE : std_logic_vector(3 downto 0); signal MEM2_TRISTATE : std_logic_vector(3 downto 0); signal MEM3_TRISTATE : std_logic_vector(3 downto 0); signal N_03612744 : std_logic_vector(3 downto 0); signal N_03614871 : std_logic_vector(3 downto 0); signal N_03615276 : std_logic_vector(3 downto 0); signal local_SVIC_REGION : std_logic_vector(3 downto 0); signal local_BS_MB0 : std_logic_vector(2 downto 0); signal local_BS_MB1 : std_logic_vector(2 downto 0); signal local_BS_MB2 : std_logic_vector(2 downto 0); signal local_BS_MB3 : std_logic_vector(2 downto 0); signal N_03614221 : std_logic_vector(2 downto 0); signal local_G_MB0 : std_logic_vector(1 downto 0); signal G_MB0_INT : std_logic_vector(1 downto 0); signal local_G_MB1 : std_logic_vector(1 downto 0); signal G_MB1_INT : std_logic_vector(1 downto 0); signal local_G_MB2 : std_logic_vector(1 downto 0); signal G_MB2_INT : std_logic_vector(1 downto 0); signal local_G_MB3 : std_logic_vector(1 downto 0); signal G_MB3_INT : std_logic_vector(1 downto 0); signal N_03625 : std_logic_vector(1 downto 0); signal local_SE3_MB0 : std_logic_vector(1 downto 0); signal local_SE3_MB1 : std_logic_vector(1 downto 0); signal local_SE3_MB2 : std_logic_vector(1 downto 0); signal local_SE3_MB3 : std_logic_vector(1 downto 0); signal local_CLEAR_OUT : std_logic; signal CLK : std_logic; signal local_CLK_DATA : std_logic; signal local_CLK_LD : std_logic; signal local_CLK_LD_CLK : std_logic; signal GSRNET : std_logic; signal local_LEMO1 : std_logic; signal local_LEMO2 : std_logic; signal local_LEMO3 : std_logic; signal local_OUTFIFO_MRSB : std_logic; signal local_OUTFIFO_OENB : std_logic; signal local_OUTFIFO_RENB : std_logic; signal local_OUTFIFO_RTB : std_logic; signal local_OUTFIFO_WENB : std_logic; signal local_RSFIFO_MRSB : std_logic; signal local_RSFIFO_OENB : std_logic; signal local_RSFIFO_RENB : std_logic; signal local_RSFIFO_RTB : std_logic; signal local_RSFIFO_WENB : std_logic; signal local_SLOW_CLK_OUT : std_logic; signal local_SPARE_OUT1 : std_logic; signal local_SPARE_OUT2 : std_logic; signal local_SVIC_LACK_N : std_logic; signal local_SVIC_LIRQ : std_logic; signal local_SW_MB0 : std_logic; signal SW_MB0_INT : std_logic; signal local_SW_MB1 : std_logic; signal SW_MB1_INT : std_logic; signal local_SW_MB2 : std_logic; signal SW_MB2_INT : std_logic; signal local_SW_MB3 : std_logic; signal SW_MB3_INT : std_logic; signal local_S_DATA_OUT : std_logic; signal local_VME_XCVR_LDS : std_logic; signal local_VME_XCVR_MWB_N : std_logic; signal local_VME_XCVR_STROBE_N : std_logic; signal clear_fifo_A : std_logic; signal clear_fifo_B : std_logic; signal empty_A : std_logic; signal empty_B : std_logic; signal full_A : std_logic; signal full_B : std_logic; signal outfifo_efB_int : std_logic; signal outfifo_ffB_int : std_logic; signal outfifo_mrsB_int : std_logic; signal outfifo_oenB_int : std_logic; signal outfifo_renB_int : std_logic; signal outfifo_rtB_int : std_logic; signal outfifo_wenB_int : std_logic; signal read_A : std_logic; signal read_B : std_logic; signal read_TV_data : std_logic; signal receive_TV_data : std_logic; signal reset_resync_fifo : std_logic; signal rsfifo_efb_int : std_logic; signal rsfifo_ffb_int : std_logic; signal rsfifo_mrsb_int : std_logic; signal rsfifo_oenb_int : std_logic; signal rsfifo_renb_int : std_logic; signal rsfifo_rtb_int : std_logic; signal rsfifo_wenb_int : std_logic; signal wren_A : std_logic; signal wren_B : std_logic; signal write_A : std_logic; signal write_B : std_logic; signal N_03610002 : std_logic; signal N_03610005 : std_logic; signal N_03610008 : std_logic; signal N_03610012 : std_logic; signal N_03610015 : std_logic; signal N_03610018 : std_logic; signal N_03610021 : std_logic; signal N_03610024 : std_logic; signal N_03610027 : std_logic; signal N_03610030 : std_logic; signal N_03610033 : std_logic; signal N_03610036 : std_logic; signal N_03610039 : std_logic; signal N_03610042 : std_logic; signal N_03610045 : std_logic; signal N_03610047 : std_logic; signal N_03610048 : std_logic; signal N_03610050 : std_logic; signal N_03610258 : std_logic; signal N_03610260 : std_logic; signal N_03610265 : std_logic; signal N_03610268 : std_logic; signal N_03610271 : std_logic; signal N_03610274 : std_logic; signal N_03610282 : std_logic; signal N_03610288 : std_logic; signal N_03610294 : std_logic; signal N_03610300 : std_logic; signal N_03610306 : std_logic; signal N_03610312 : std_logic; signal N_03610318 : std_logic; signal N_03610324 : std_logic; signal N_03610336 : std_logic; signal N_03610341 : std_logic; signal N_03610342 : std_logic; signal N_03610343 : std_logic; signal N_03610349 : std_logic; signal N_03610351 : std_logic; signal N_03610353 : std_logic; signal N_03610355 : std_logic; signal N_03610357 : std_logic; signal N_03610359 : std_logic; signal N_03610361 : std_logic; signal N_03610363 : std_logic; signal N_03610365 : std_logic; signal N_03610367 : std_logic; signal N_03610368 : std_logic; signal N_03610370 : std_logic; signal N_03610372 : std_logic; signal N_03610374 : std_logic; signal N_03610376 : std_logic; signal N_03610378 : std_logic; signal N_03610380 : std_logic; signal N_03610382 : std_logic; signal N_03610384 : std_logic; signal N_03610386 : std_logic; signal N_03610388 : std_logic; signal N_03610390 : std_logic; signal N_03610392 : std_logic; signal N_03610394 : std_logic; signal N_03610417 : std_logic; signal N_03610421 : std_logic; signal N_03610422 : std_logic; signal N_03610425 : std_logic; signal N_03610426 : std_logic; signal N_03610427 : std_logic; signal N_03610430 : std_logic; signal N_03610432 : std_logic; signal N_03610436 : std_logic; signal N_03610440 : std_logic; signal N_03610441 : std_logic; signal N_03610450 : std_logic; signal N_03610451 : std_logic; signal N_03610455 : std_logic; signal N_03610456 : std_logic; signal N_03610460 : std_logic; signal N_03610461 : std_logic; signal N_03610465 : std_logic; signal N_03610466 : std_logic; signal N_03610470 : std_logic; signal N_03610471 : std_logic; signal N_03610476 : std_logic; signal N_03610477 : std_logic; signal N_03610481 : std_logic; signal N_03610482 : std_logic; signal N_03610486 : std_logic; signal N_03610487 : std_logic; signal N_03610491 : std_logic; signal N_03610492 : std_logic; signal N_03610501 : std_logic; signal N_03610502 : std_logic; signal N_03610506 : std_logic; signal N_03610507 : std_logic; signal N_03610511 : std_logic; signal N_03610512 : std_logic; signal N_03610516 : std_logic; signal N_03610517 : std_logic; signal N_03610521 : std_logic; signal N_03610522 : std_logic; signal N_03610527 : std_logic; signal N_03610528 : std_logic; signal N_03610532 : std_logic; signal N_03610533 : std_logic; signal N_03610537 : std_logic; signal N_03610538 : std_logic; signal N_03610542 : std_logic; signal N_03610543 : std_logic; signal N_03610552 : std_logic; signal N_03610553 : std_logic; signal N_03610557 : std_logic; signal N_03610558 : std_logic; signal N_03610562 : std_logic; signal N_03610563 : std_logic; signal N_03610567 : std_logic; signal N_03610568 : std_logic; signal N_03610572 : std_logic; signal N_03610573 : std_logic; signal N_03610578 : std_logic; signal N_03610579 : std_logic; signal N_03610583 : std_logic; signal N_03610584 : std_logic; signal N_03610588 : std_logic; signal N_03610589 : std_logic; signal N_03610593 : std_logic; signal N_03610594 : std_logic; signal N_03610603 : std_logic; signal N_03610604 : std_logic; signal N_03610608 : std_logic; signal N_03610609 : std_logic; signal N_03610613 : std_logic; signal N_03610614 : std_logic; signal N_03610618 : std_logic; signal N_03610619 : std_logic; signal N_03610623 : std_logic; signal N_03610624 : std_logic; signal N_03610629 : std_logic; signal N_03610630 : std_logic; signal N_03610634 : std_logic; signal N_03610635 : std_logic; signal N_03610639 : std_logic; signal N_03610640 : std_logic; signal N_03610643 : std_logic; signal N_03610644 : std_logic; signal N_03610645 : std_logic; signal N_03610646 : std_logic; signal N_03610647 : std_logic; signal N_03610648 : std_logic; signal N_03610649 : std_logic; signal N_03610650 : std_logic; signal N_03610651 : std_logic; signal N_03610652 : std_logic; signal N_03610653 : std_logic; signal N_03610654 : std_logic; signal N_03610655 : std_logic; signal N_03610656 : std_logic; signal N_03610657 : std_logic; signal N_03610658 : std_logic; signal N_03610659 : std_logic; signal N_03610660 : std_logic; signal N_03610661 : std_logic; signal N_03610662 : std_logic; signal N_03610663 : std_logic; signal N_03610664 : std_logic; signal N_03610665 : std_logic; signal N_03610666 : std_logic; signal N_03610667 : std_logic; signal N_03610668 : std_logic; signal N_03610669 : std_logic; signal N_03610670 : std_logic; signal N_03610671 : std_logic; signal N_03610672 : std_logic; signal N_03610673 : std_logic; signal N_03610674 : std_logic; signal N_03610675 : std_logic; signal N_03610676 : std_logic; signal N_03610677 : std_logic; signal N_03610678 : std_logic; signal N_03610679 : std_logic; signal N_03610680 : std_logic; signal N_03610681 : std_logic; signal N_03610682 : std_logic; signal N_03610683 : std_logic; signal N_03610684 : std_logic; signal N_03610685 : std_logic; signal N_03610686 : std_logic; signal N_03610687 : std_logic; signal N_03610688 : std_logic; signal N_03610689 : std_logic; signal N_03610690 : std_logic; signal N_03610691 : std_logic; signal N_03610692 : std_logic; signal N_03610693 : std_logic; signal N_03610694 : std_logic; signal N_03610695 : std_logic; signal N_03610696 : std_logic; signal N_03610697 : std_logic; signal N_03610698 : std_logic; signal N_03610699 : std_logic; signal N_03610700 : std_logic; signal N_03610701 : std_logic; signal N_03610702 : std_logic; signal N_03610703 : std_logic; signal N_03610704 : std_logic; signal N_03610705 : std_logic; signal N_03610706 : std_logic; signal N_03610707 : std_logic; signal N_03610708 : std_logic; signal N_03610709 : std_logic; signal N_03610710 : std_logic; signal N_03610711 : std_logic; signal N_03610712 : std_logic; signal N_03610713 : std_logic; signal N_03610714 : std_logic; signal N_03612318 : std_logic; signal N_03612520 : std_logic; signal N_03612521 : std_logic; signal N_03612522 : std_logic; signal N_03612523 : std_logic; signal N_03612524 : std_logic; signal N_03612525 : std_logic; signal N_03612526 : std_logic; signal N_03612527 : std_logic; signal N_03612528 : std_logic; signal N_03612529 : std_logic; signal N_03613043 : std_logic; signal N_03613046 : std_logic; signal N_03613047 : std_logic; signal N_03613048 : std_logic; signal N_03613476 : std_logic; signal N_03613481 : std_logic; signal N_03613484 : std_logic; signal N_03613485 : std_logic; signal N_03613511 : std_logic; signal N_03613713 : std_logic; signal N_03613715 : std_logic; signal N_03613717 : std_logic; signal N_03613726 : std_logic; signal N_03613727 : std_logic; signal N_03613730 : std_logic; signal N_03613737 : std_logic; signal N_03613943 : std_logic; signal N_03613946 : std_logic; signal N_03613950 : std_logic; signal N_03613952 : std_logic; signal N_03614218 : std_logic; signal N_03614231 : std_logic; signal N_03614240 : std_logic; signal N_03614241 : std_logic; signal N_03614248 : std_logic; signal N_03614453 : std_logic; signal N_03614454 : std_logic; signal N_03614455 : std_logic; signal N_03616492 : std_logic; signal N_03617237 : std_logic; signal N_03617239 : std_logic; signal N_03617240 : std_logic; signal N_03617241 : std_logic; signal N_03617242 : std_logic; signal N_03617258 : std_logic; signal N_03617259 : std_logic; signal N_03617260 : std_logic; signal N_03617261 : std_logic; signal N_03617262 : std_logic; signal N_03617263 : std_logic; signal N_03617264 : std_logic; signal N_03617265 : std_logic; signal N_03617273 : std_logic; signal N_03617281 : std_logic; signal N_03617282 : std_logic; signal N_03617283 : std_logic; signal N_03617328 : std_logic; signal N_03617329 : std_logic; signal N_03617330 : std_logic; signal N_03617331 : std_logic; signal N_03617332 : std_logic; signal N_03617333 : std_logic; signal N_03617334 : std_logic; signal N_03617335 : std_logic; signal N_03617340 : std_logic; signal N_03617342 : std_logic; signal N_03617350 : std_logic; signal N_03617351 : std_logic; signal N_03617352 : std_logic; signal N_03617353 : std_logic; signal N_03617365 : std_logic; signal N_03617366 : std_logic; signal N_03617367 : std_logic; signal N_0363584 : std_logic; signal N_0365513 : std_logic; signal N_0365548 : std_logic; signal N_0365549 : std_logic; signal N_0365550 : std_logic; signal N_0365551 : std_logic; signal N_0365552 : std_logic; signal N_0365553 : std_logic; signal N_0365554 : std_logic; signal N_0365555 : std_logic; signal N_0365556 : std_logic; signal N_0365557 : std_logic; signal N_0365558 : std_logic; signal N_0365559 : std_logic; signal N_0365560 : std_logic; signal N_0365561 : std_logic; signal N_0365562 : std_logic; signal N_0365563 : std_logic; signal N_0365564 : std_logic; signal N_0365566 : std_logic; signal N_0365567 : std_logic; signal N_0365576 : std_logic; signal N_0365577 : std_logic; signal N_0365581 : std_logic; signal N_0365582 : std_logic; signal N_0365586 : std_logic; signal N_0365587 : std_logic; signal N_0365591 : std_logic; signal N_0365592 : std_logic; signal N_0365596 : std_logic; signal N_0365597 : std_logic; signal N_0365602 : std_logic; signal N_0365603 : std_logic; signal N_0365607 : std_logic; signal N_0365608 : std_logic; signal N_0365612 : std_logic; signal N_0365613 : std_logic; signal N_0365617 : std_logic; signal N_0365618 : std_logic; signal N_0365627 : std_logic; signal N_0365628 : std_logic; signal N_0365632 : std_logic; signal N_0365633 : std_logic; signal N_0365637 : std_logic; signal N_0365638 : std_logic; signal N_0365642 : std_logic; signal N_0365643 : std_logic; signal N_0365647 : std_logic; signal N_0365648 : std_logic; signal N_0365653 : std_logic; signal N_0365654 : std_logic; signal N_0365658 : std_logic; signal N_0365659 : std_logic; signal N_0365663 : std_logic; signal N_0365664 : std_logic; signal N_0365668 : std_logic; signal N_0365669 : std_logic; signal N_0365678 : std_logic; signal N_0365679 : std_logic; signal N_0365683 : std_logic; signal N_0365684 : std_logic; signal N_0365688 : std_logic; signal N_0365689 : std_logic; signal N_0365693 : std_logic; signal N_0365694 : std_logic; signal N_0365698 : std_logic; signal N_0365699 : std_logic; signal N_0365704 : std_logic; signal N_0365705 : std_logic; signal N_0365709 : std_logic; signal N_0365710 : std_logic; signal N_0365714 : std_logic; signal N_0365715 : std_logic; signal N_0365719 : std_logic; signal N_0365720 : std_logic; signal N_0365729 : std_logic; signal N_0365730 : std_logic; signal N_0365734 : std_logic; signal N_0365735 : std_logic; signal N_0365739 : std_logic; signal N_0365740 : std_logic; signal N_0365744 : std_logic; signal N_0365745 : std_logic; signal N_0365749 : std_logic; signal N_0365750 : std_logic; signal N_0365755 : std_logic; signal N_0365756 : std_logic; signal N_0365760 : std_logic; signal N_0365761 : std_logic; signal N_0365765 : std_logic; signal N_0365766 : std_logic; signal N_0365769 : std_logic; signal N_0365770 : std_logic; signal N_0365771 : std_logic; signal N_0365772 : std_logic; signal N_0365773 : std_logic; signal N_0365774 : std_logic; signal N_0365775 : std_logic; signal N_0365776 : std_logic; signal N_0365777 : std_logic; signal N_0365778 : std_logic; signal N_0365779 : std_logic; signal N_0365780 : std_logic; signal N_0365781 : std_logic; signal N_0365782 : std_logic; signal N_0365783 : std_logic; signal N_0365784 : std_logic; signal N_0365785 : std_logic; signal N_0365786 : std_logic; signal N_0365787 : std_logic; signal N_0365788 : std_logic; signal N_0365789 : std_logic; signal N_0365790 : std_logic; signal N_0365791 : std_logic; signal N_0365792 : std_logic; signal N_0365793 : std_logic; signal N_0365794 : std_logic; signal N_0365795 : std_logic; signal N_0365796 : std_logic; signal N_0365797 : std_logic; signal N_0365798 : std_logic; signal N_0365799 : std_logic; signal N_0365800 : std_logic; signal N_0365801 : std_logic; signal N_0365802 : std_logic; signal N_0365803 : std_logic; signal N_0365804 : std_logic; signal N_0365805 : std_logic; signal N_0365806 : std_logic; signal N_0365807 : std_logic; signal N_0365808 : std_logic; signal N_0365809 : std_logic; signal N_0365810 : std_logic; signal N_0365811 : std_logic; signal N_0365812 : std_logic; signal N_0365813 : std_logic; signal N_0365814 : std_logic; signal N_0365815 : std_logic; signal N_0365816 : std_logic; signal N_0365817 : std_logic; signal N_0365818 : std_logic; signal N_0365819 : std_logic; signal N_0365820 : std_logic; signal N_0365821 : std_logic; signal N_0365822 : std_logic; signal N_0365823 : std_logic; signal N_0365824 : std_logic; signal N_0365825 : std_logic; signal N_0365826 : std_logic; signal N_0365827 : std_logic; signal N_0365828 : std_logic; signal N_0365829 : std_logic; signal N_0365830 : std_logic; signal N_0365831 : std_logic; signal N_0365832 : std_logic; signal N_0365833 : std_logic; signal N_0365834 : std_logic; signal N_0365835 : std_logic; signal N_0365836 : std_logic; signal N_0365837 : std_logic; signal N_0365838 : std_logic; signal N_0365839 : std_logic; signal N_0365840 : std_logic; signal N_036626 : std_logic; signal N_0367669 : std_logic; signal N_0367672 : std_logic; signal N_0367675 : std_logic; signal N_0367678 : std_logic; signal N_0367681 : std_logic; signal N_0367684 : std_logic; signal N_0367688 : std_logic; signal N_0367691 : std_logic; signal N_0367694 : std_logic; signal N_0367697 : std_logic; signal N_0367700 : std_logic; signal N_0367703 : std_logic; signal N_0367706 : std_logic; signal N_0367709 : std_logic; signal N_0367712 : std_logic; signal N_0367715 : std_logic; signal N_0367718 : std_logic; signal N_0367721 : std_logic; signal N_0367724 : std_logic; signal N_0367727 : std_logic; signal N_0367730 : std_logic; signal N_0367733 : std_logic; signal N_0367736 : std_logic; signal N_0367739 : std_logic; signal N_0367742 : std_logic; signal N_0367745 : std_logic; signal N_0367748 : std_logic; signal N_0367751 : std_logic; signal N_0367754 : std_logic; signal N_0367757 : std_logic; signal N_0367760 : std_logic; signal N_0367763 : std_logic; signal N_0367766 : std_logic; signal N_0367769 : std_logic; signal N_0367772 : std_logic; signal N_0367775 : std_logic; signal N_0367777 : std_logic; signal N_0367779 : std_logic; signal N_0367785 : std_logic; signal N_0367789 : std_logic; signal N_0367790 : std_logic; signal N_0367792 : std_logic; signal N_0368001 : std_logic; signal N_0368003 : std_logic; signal N_0368266 : std_logic; signal N_0368267 : std_logic; signal N_0368271 : std_logic; signal N_0368272 : std_logic; signal N_0369093 : std_logic; signal N_0369096 : std_logic; signal N_0369097 : std_logic; signal N_0369100 : std_logic; signal N_0369101 : std_logic; signal N_0369106 : std_logic; signal N_0369312 : std_logic; signal N_0369517 : std_logic; signal N_0369722 : std_logic; signal N_0369929 : std_logic; signal N_0369932 : std_logic; signal N_0369935 : std_logic; signal N_0369938 : std_logic; signal N_0369941 : std_logic; signal N_0369944 : std_logic; signal N_0369948 : std_logic; signal N_0369951 : std_logic; signal N_0369954 : std_logic; signal N_0369957 : std_logic; signal N_0369960 : std_logic; signal N_0369963 : std_logic; signal N_0369966 : std_logic; signal N_0369969 : std_logic; signal N_0369972 : std_logic; signal N_0369975 : std_logic; signal N_0369978 : std_logic; signal N_0369981 : std_logic; signal N_0369983 : std_logic; signal N_0369984 : std_logic; signal N_0369986 : std_logic; signal N_0369993 : std_logic; signal N_0369996 : std_logic; signal N_0369999 : std_logic; alias N_0365510 : std_logic is FIFO_OUT_INT(( 0 )); alias N_0365519 : std_logic is FIFO_OUT_INT(( 1 )); alias N_0365520 : std_logic is FIFO_OUT_INT(( 2 )); alias N_0365521 : std_logic is FIFO_OUT_INT(( 3 )); alias N_0365522 : std_logic is FIFO_OUT_INT(( 4 )); alias N_0365523 : std_logic is FIFO_OUT_INT(( 5 )); alias N_0365524 : std_logic is FIFO_OUT_INT(( 6 )); alias N_0365531 : std_logic is FIFO_OUT_INT(( 7 )); alias N_0365532 : std_logic is FIFO_OUT_INT(( 8 )); alias N_0365533 : std_logic is FIFO_OUT_INT(( 9 )); alias N_0365534 : std_logic is FIFO_OUT_INT(( 10 )); alias N_0365535 : std_logic is FIFO_OUT_INT(( 11 )); alias N_0365536 : std_logic is FIFO_OUT_INT(( 12 )); alias N_0365538 : std_logic is FIFO_OUT_INT(( 13 )); alias N_0365540 : std_logic is FIFO_OUT_INT(( 14 )); alias N_0365542 : std_logic is FIFO_OUT_INT(( 15 )); alias N_0365544 : std_logic is FIFO_OUT_INT(( 16 )); alias N_0365546 : std_logic is FIFO_OUT_INT(( 17 )); alias N_0368478 : std_logic is G_MB0_INT(( 0 )); alias N_0368479 : std_logic is G_MB0_INT(1); alias N_0368476 : std_logic is G_MB1_INT(( 0 )); alias N_0368477 : std_logic is G_MB1_INT(1); alias N_03610263 : std_logic is G_MB2_INT(( 0 )); alias N_03610266 : std_logic is G_MB2_INT(1); alias N_03610269 : std_logic is G_MB3_INT(( 0 )); alias N_03610272 : std_logic is G_MB3_INT(1); alias N_0367399 : std_logic is MEM0_TRISTATE(0); alias N_0367402 : std_logic is MEM0_TRISTATE(2); alias N_0367404 : std_logic is MEM0_TRISTATE(3); alias N_0367406 : std_logic is MEM0_TRISTATE(1); alias N_0365721 : std_logic is MEM1_TRISTATE(( 0 )); alias N_0365751 : std_logic is MEM1_TRISTATE(1); alias N_0367194 : std_logic is MEM1_TRISTATE(2); alias N_0367197 : std_logic is MEM1_TRISTATE(3); alias N_03610442 : std_logic is MEM2_TRISTATE(2); alias N_03610472 : std_logic is MEM2_TRISTATE(3); alias N_03610493 : std_logic is MEM2_TRISTATE(0); alias N_03610523 : std_logic is MEM2_TRISTATE(1); alias N_03610544 : std_logic is MEM3_TRISTATE(2); alias N_03610574 : std_logic is MEM3_TRISTATE(3); alias N_03610595 : std_logic is MEM3_TRISTATE(( 0 )); alias N_03610625 : std_logic is MEM3_TRISTATE(1); alias N_0367666 : std_logic is MEM_ADDR_MB0_INT(( 0 )); alias N_0367670 : std_logic is MEM_ADDR_MB0_INT(( 1 )); alias N_0367673 : std_logic is MEM_ADDR_MB0_INT(( 2 )); alias N_0367676 : std_logic is MEM_ADDR_MB0_INT(( 3 )); alias N_0367679 : std_logic is MEM_ADDR_MB0_INT(( 4 )); alias N_0367682 : std_logic is MEM_ADDR_MB0_INT(( 5 )); alias N_0367686 : std_logic is MEM_ADDR_MB0_INT(( 6 )); alias N_0367689 : std_logic is MEM_ADDR_MB0_INT(( 7 )); alias N_0367692 : std_logic is MEM_ADDR_MB0_INT(( 8 )); alias N_0367695 : std_logic is MEM_ADDR_MB0_INT(( 9 )); alias N_0367698 : std_logic is MEM_ADDR_MB0_INT(( 10 )); alias N_0367701 : std_logic is MEM_ADDR_MB0_INT(( 11 )); alias N_0367704 : std_logic is MEM_ADDR_MB0_INT(( 12 )); alias N_0367707 : std_logic is MEM_ADDR_MB0_INT(( 13 )); alias N_0367710 : std_logic is MEM_ADDR_MB0_INT(( 14 )); alias N_0367713 : std_logic is MEM_ADDR_MB0_INT(( 15 )); alias N_0367716 : std_logic is MEM_ADDR_MB0_INT(( 16 )); alias N_0367719 : std_logic is MEM_ADDR_MB0_INT(( 17 )); alias N_0367788 : std_logic is MEM_ADDR_MB0_INT(( 18)); alias N_0367794 : std_logic is MEM_ADDR_MB0_INT(( 18)); alias N_0367722 : std_logic is MEM_ADDR_MB1_INT(( 0 )); alias N_0367725 : std_logic is MEM_ADDR_MB1_INT(( 1 )); alias N_0367728 : std_logic is MEM_ADDR_MB1_INT(( 2 )); alias N_0367731 : std_logic is MEM_ADDR_MB1_INT(( 3 )); alias N_0367734 : std_logic is MEM_ADDR_MB1_INT(( 4 )); alias N_0367737 : std_logic is MEM_ADDR_MB1_INT(( 5 )); alias N_0367740 : std_logic is MEM_ADDR_MB1_INT(( 6 )); alias N_0367743 : std_logic is MEM_ADDR_MB1_INT(( 7 )); alias N_0367746 : std_logic is MEM_ADDR_MB1_INT(( 8 )); alias N_0367749 : std_logic is MEM_ADDR_MB1_INT(( 9 )); alias N_0367752 : std_logic is MEM_ADDR_MB1_INT(( 10 )); alias N_0367755 : std_logic is MEM_ADDR_MB1_INT(( 11 )); alias N_0367758 : std_logic is MEM_ADDR_MB1_INT(( 12 )); alias N_0367761 : std_logic is MEM_ADDR_MB1_INT(( 13 )); alias N_0367764 : std_logic is MEM_ADDR_MB1_INT(( 14 )); alias N_0367767 : std_logic is MEM_ADDR_MB1_INT(( 15 )); alias N_0367770 : std_logic is MEM_ADDR_MB1_INT(( 16 )); alias N_0367773 : std_logic is MEM_ADDR_MB1_INT(( 17 )); alias N_0367778 : std_logic is MEM_ADDR_MB1_INT(( 18)); alias N_0367783 : std_logic is MEM_ADDR_MB1_INT(( 18)); alias N_0369926 : std_logic is MEM_ADDR_MB2_INT(( 0 )); alias N_0369930 : std_logic is MEM_ADDR_MB2_INT(( 1 )); alias N_0369933 : std_logic is MEM_ADDR_MB2_INT(( 2 )); alias N_0369936 : std_logic is MEM_ADDR_MB2_INT(( 3 )); alias N_0369939 : std_logic is MEM_ADDR_MB2_INT(( 4 )); alias N_0369942 : std_logic is MEM_ADDR_MB2_INT(( 5 )); alias N_0369946 : std_logic is MEM_ADDR_MB2_INT(( 6 )); alias N_0369949 : std_logic is MEM_ADDR_MB2_INT(( 7 )); alias N_0369952 : std_logic is MEM_ADDR_MB2_INT(( 8 )); alias N_0369955 : std_logic is MEM_ADDR_MB2_INT(( 9 )); alias N_0369958 : std_logic is MEM_ADDR_MB2_INT(( 10 )); alias N_0369961 : std_logic is MEM_ADDR_MB2_INT(( 11 )); alias N_0369964 : std_logic is MEM_ADDR_MB2_INT(( 12 )); alias N_0369967 : std_logic is MEM_ADDR_MB2_INT(( 13 )); alias N_0369970 : std_logic is MEM_ADDR_MB2_INT(( 14 )); alias N_0369973 : std_logic is MEM_ADDR_MB2_INT(( 15 )); alias N_0369976 : std_logic is MEM_ADDR_MB2_INT(( 16 )); alias N_0369979 : std_logic is MEM_ADDR_MB2_INT(( 17 )); alias N_0369982 : std_logic is MEM_ADDR_MB2_INT(( 18)); alias N_0369987 : std_logic is MEM_ADDR_MB2_INT(( 18)); alias N_03610000 : std_logic is MEM_ADDR_MB3_INT(( 3 )); alias N_03610003 : std_logic is MEM_ADDR_MB3_INT(( 4 )); alias N_03610006 : std_logic is MEM_ADDR_MB3_INT(( 5 )); alias N_03610010 : std_logic is MEM_ADDR_MB3_INT(( 6 )); alias N_03610013 : std_logic is MEM_ADDR_MB3_INT(( 7 )); alias N_03610016 : std_logic is MEM_ADDR_MB3_INT(( 8 )); alias N_03610019 : std_logic is MEM_ADDR_MB3_INT(( 9 )); alias N_03610022 : std_logic is MEM_ADDR_MB3_INT(( 10 )); alias N_03610025 : std_logic is MEM_ADDR_MB3_INT(( 11 )); alias N_03610028 : std_logic is MEM_ADDR_MB3_INT(( 12 )); alias N_03610031 : std_logic is MEM_ADDR_MB3_INT(( 13 )); alias N_03610034 : std_logic is MEM_ADDR_MB3_INT(( 14 )); alias N_03610037 : std_logic is MEM_ADDR_MB3_INT(( 15 )); alias N_03610040 : std_logic is MEM_ADDR_MB3_INT(( 16 )); alias N_03610043 : std_logic is MEM_ADDR_MB3_INT(( 17 )); alias N_03610046 : std_logic is MEM_ADDR_MB3_INT(( 18)); alias N_03610051 : std_logic is MEM_ADDR_MB3_INT(( 18)); alias N_0369990 : std_logic is MEM_ADDR_MB3_INT(( 0 )); alias N_0369994 : std_logic is MEM_ADDR_MB3_INT(( 1 )); alias N_0369997 : std_logic is MEM_ADDR_MB3_INT(( 2 )); alias N_0365571 : std_logic is MEM_DATAH_MB0_I(( 0 )); alias N_0365579 : std_logic is MEM_DATAH_MB0_I(( 1 )); alias N_0365584 : std_logic is MEM_DATAH_MB0_I(( 2 )); alias N_0365589 : std_logic is MEM_DATAH_MB0_I(( 3 )); alias N_0365594 : std_logic is MEM_DATAH_MB0_I(( 4 )); alias N_0365600 : std_logic is MEM_DATAH_MB0_I(( 5 )); alias N_0365605 : std_logic is MEM_DATAH_MB0_I(( 6 )); alias N_0365610 : std_logic is MEM_DATAH_MB0_I(( 7 )); alias N_0365615 : std_logic is MEM_DATAH_MB0_I(( 8 )); alias N_0365569 : std_logic is MEM_DATAH_MB0_O(( 0 )); alias N_0365578 : std_logic is MEM_DATAH_MB0_O(( 1 )); alias N_0365583 : std_logic is MEM_DATAH_MB0_O(( 2 )); alias N_0365588 : std_logic is MEM_DATAH_MB0_O(( 3 )); alias N_0365593 : std_logic is MEM_DATAH_MB0_O(( 4 )); alias N_0365599 : std_logic is MEM_DATAH_MB0_O(( 5 )); alias N_0365604 : std_logic is MEM_DATAH_MB0_O(( 6 )); alias N_0365609 : std_logic is MEM_DATAH_MB0_O(( 7 )); alias N_0365614 : std_logic is MEM_DATAH_MB0_O(( 8 )); alias N_0365674 : std_logic is MEM_DATAH_MB1_I(( 0 )); alias N_0365681 : std_logic is MEM_DATAH_MB1_I(( 1 )); alias N_0365686 : std_logic is MEM_DATAH_MB1_I(( 2 )); alias N_0365691 : std_logic is MEM_DATAH_MB1_I(( 3 )); alias N_0365696 : std_logic is MEM_DATAH_MB1_I(( 4 )); alias N_0365702 : std_logic is MEM_DATAH_MB1_I(( 5 )); alias N_0365707 : std_logic is MEM_DATAH_MB1_I(( 6 )); alias N_0365712 : std_logic is MEM_DATAH_MB1_I(( 7 )); alias N_0365717 : std_logic is MEM_DATAH_MB1_I(( 8 )); alias N_0365672 : std_logic is MEM_DATAH_MB1_O(( 0 )); alias N_0365680 : std_logic is MEM_DATAH_MB1_O(( 1 )); alias N_0365685 : std_logic is MEM_DATAH_MB1_O(( 2 )); alias N_0365690 : std_logic is MEM_DATAH_MB1_O(( 3 )); alias N_0365695 : std_logic is MEM_DATAH_MB1_O(( 4 )); alias N_0365701 : std_logic is MEM_DATAH_MB1_O(( 5 )); alias N_0365706 : std_logic is MEM_DATAH_MB1_O(( 6 )); alias N_0365711 : std_logic is MEM_DATAH_MB1_O(( 7 )); alias N_0365716 : std_logic is MEM_DATAH_MB1_O(( 8 )); alias N_03610445 : std_logic is MEM_DATAH_MB2_I(( 0 )); alias N_03610453 : std_logic is MEM_DATAH_MB2_I(( 1 )); alias N_03610458 : std_logic is MEM_DATAH_MB2_I(( 2 )); alias N_03610463 : std_logic is MEM_DATAH_MB2_I(( 3 )); alias N_03610468 : std_logic is MEM_DATAH_MB2_I(( 4 )); alias N_03610474 : std_logic is MEM_DATAH_MB2_I(( 5 )); alias N_03610479 : std_logic is MEM_DATAH_MB2_I(( 6 )); alias N_03610484 : std_logic is MEM_DATAH_MB2_I(( 7 )); alias N_03610489 : std_logic is MEM_DATAH_MB2_I(( 8 )); alias N_03610443 : std_logic is MEM_DATAH_MB2_O(( 0 )); alias N_03610452 : std_logic is MEM_DATAH_MB2_O(( 1 )); alias N_03610457 : std_logic is MEM_DATAH_MB2_O(( 2 )); alias N_03610462 : std_logic is MEM_DATAH_MB2_O(( 3 )); alias N_03610467 : std_logic is MEM_DATAH_MB2_O(( 4 )); alias N_03610473 : std_logic is MEM_DATAH_MB2_O(( 5 )); alias N_03610478 : std_logic is MEM_DATAH_MB2_O(( 6 )); alias N_03610483 : std_logic is MEM_DATAH_MB2_O(( 7 )); alias N_03610488 : std_logic is MEM_DATAH_MB2_O(( 8 )); alias N_03610548 : std_logic is MEM_DATAH_MB3_I(( 0 )); alias N_03610555 : std_logic is MEM_DATAH_MB3_I(( 1 )); alias N_03610560 : std_logic is MEM_DATAH_MB3_I(( 2 )); alias N_03610565 : std_logic is MEM_DATAH_MB3_I(( 3 )); alias N_03610570 : std_logic is MEM_DATAH_MB3_I(( 4 )); alias N_03610576 : std_logic is MEM_DATAH_MB3_I(( 5 )); alias N_03610581 : std_logic is MEM_DATAH_MB3_I(( 6 )); alias N_03610586 : std_logic is MEM_DATAH_MB3_I(( 7 )); alias N_03610591 : std_logic is MEM_DATAH_MB3_I(( 8 )); alias N_03610546 : std_logic is MEM_DATAH_MB3_O(( 0 )); alias N_03610554 : std_logic is MEM_DATAH_MB3_O(( 1 )); alias N_03610559 : std_logic is MEM_DATAH_MB3_O(( 2 )); alias N_03610564 : std_logic is MEM_DATAH_MB3_O(( 3 )); alias N_03610569 : std_logic is MEM_DATAH_MB3_O(( 4 )); alias N_03610575 : std_logic is MEM_DATAH_MB3_O(( 5 )); alias N_03610580 : std_logic is MEM_DATAH_MB3_O(( 6 )); alias N_03610585 : std_logic is MEM_DATAH_MB3_O(( 7 )); alias N_03610590 : std_logic is MEM_DATAH_MB3_O(( 8 )); alias N_0365623 : std_logic is MEM_DATAL_MB0_I(( 0 )); alias N_0365630 : std_logic is MEM_DATAL_MB0_I(( 1 )); alias N_0365635 : std_logic is MEM_DATAL_MB0_I(( 2 )); alias N_0365640 : std_logic is MEM_DATAL_MB0_I(( 3 )); alias N_0365645 : std_logic is MEM_DATAL_MB0_I(( 4 )); alias N_0365651 : std_logic is MEM_DATAL_MB0_I(( 5 )); alias N_0365656 : std_logic is MEM_DATAL_MB0_I(( 6 )); alias N_0365661 : std_logic is MEM_DATAL_MB0_I(( 7 )); alias N_0365666 : std_logic is MEM_DATAL_MB0_I(( 8 )); alias N_0365621 : std_logic is MEM_DATAL_MB0_O(( 0 )); alias N_0365629 : std_logic is MEM_DATAL_MB0_O(1); alias N_0365634 : std_logic is MEM_DATAL_MB0_O(( 2 )); alias N_0365639 : std_logic is MEM_DATAL_MB0_O(( 3 )); alias N_0365644 : std_logic is MEM_DATAL_MB0_O(( 4 )); alias N_0365650 : std_logic is MEM_DATAL_MB0_O(( 5 )); alias N_0365655 : std_logic is MEM_DATAL_MB0_O(( 6 )); alias N_0365660 : std_logic is MEM_DATAL_MB0_O(( 7 )); alias N_0365665 : std_logic is MEM_DATAL_MB0_O(( 8 )); alias N_0365725 : std_logic is MEM_DATAL_MB1_I(( 0 )); alias N_0365732 : std_logic is MEM_DATAL_MB1_I(( 1 )); alias N_0365737 : std_logic is MEM_DATAL_MB1_I(( 2 )); alias N_0365742 : std_logic is MEM_DATAL_MB1_I(( 3 )); alias N_0365747 : std_logic is MEM_DATAL_MB1_I(( 4 )); alias N_0365753 : std_logic is MEM_DATAL_MB1_I(( 5 )); alias N_0365758 : std_logic is MEM_DATAL_MB1_I(( 6 )); alias N_0365763 : std_logic is MEM_DATAL_MB1_I(( 7 )); alias N_0365768 : std_logic is MEM_DATAL_MB1_I(( 8 )); alias N_0365723 : std_logic is MEM_DATAL_MB1_O(( 0 )); alias N_0365731 : std_logic is MEM_DATAL_MB1_O(1); alias N_0365736 : std_logic is MEM_DATAL_MB1_O(( 2 )); alias N_0365741 : std_logic is MEM_DATAL_MB1_O(( 3 )); alias N_0365746 : std_logic is MEM_DATAL_MB1_O(( 4 )); alias N_0365752 : std_logic is MEM_DATAL_MB1_O(( 5 )); alias N_0365757 : std_logic is MEM_DATAL_MB1_O(( 6 )); alias N_0365762 : std_logic is MEM_DATAL_MB1_O(( 7 )); alias N_0365767 : std_logic is MEM_DATAL_MB1_O(( 8 )); alias N_03610497 : std_logic is MEM_DATAL_MB2_I(( 0 )); alias N_03610504 : std_logic is MEM_DATAL_MB2_I(( 1 )); alias N_03610509 : std_logic is MEM_DATAL_MB2_I(( 2 )); alias N_03610514 : std_logic is MEM_DATAL_MB2_I(( 3 )); alias N_03610519 : std_logic is MEM_DATAL_MB2_I(( 4 )); alias N_03610525 : std_logic is MEM_DATAL_MB2_I(( 5 )); alias N_03610530 : std_logic is MEM_DATAL_MB2_I(( 6 )); alias N_03610535 : std_logic is MEM_DATAL_MB2_I(( 7 )); alias N_03610540 : std_logic is MEM_DATAL_MB2_I(( 8 )); alias N_03610495 : std_logic is MEM_DATAL_MB2_O(( 0 )); alias N_03610503 : std_logic is MEM_DATAL_MB2_O(1); alias N_03610508 : std_logic is MEM_DATAL_MB2_O(( 2 )); alias N_03610513 : std_logic is MEM_DATAL_MB2_O(( 3 )); alias N_03610518 : std_logic is MEM_DATAL_MB2_O(( 4 )); alias N_03610524 : std_logic is MEM_DATAL_MB2_O(( 5 )); alias N_03610529 : std_logic is MEM_DATAL_MB2_O(( 6 )); alias N_03610534 : std_logic is MEM_DATAL_MB2_O(( 7 )); alias N_03610539 : std_logic is MEM_DATAL_MB2_O(( 8 )); alias N_03610599 : std_logic is MEM_DATAL_MB3_I(( 0 )); alias N_03610606 : std_logic is MEM_DATAL_MB3_I(( 1 )); alias N_03610611 : std_logic is MEM_DATAL_MB3_I(( 2 )); alias N_03610616 : std_logic is MEM_DATAL_MB3_I(( 3 )); alias N_03610621 : std_logic is MEM_DATAL_MB3_I(( 4 )); alias N_03610627 : std_logic is MEM_DATAL_MB3_I(( 5 )); alias N_03610632 : std_logic is MEM_DATAL_MB3_I(( 6 )); alias N_03610637 : std_logic is MEM_DATAL_MB3_I(( 7 )); alias N_03610642 : std_logic is MEM_DATAL_MB3_I(( 8 )); alias N_03610597 : std_logic is MEM_DATAL_MB3_O(( 0 )); alias N_03610605 : std_logic is MEM_DATAL_MB3_O(1); alias N_03610610 : std_logic is MEM_DATAL_MB3_O(( 2 )); alias N_03610615 : std_logic is MEM_DATAL_MB3_O(( 3 )); alias N_03610620 : std_logic is MEM_DATAL_MB3_O(( 4 )); alias N_03610626 : std_logic is MEM_DATAL_MB3_O(( 5 )); alias N_03610631 : std_logic is MEM_DATAL_MB3_O(( 6 )); alias N_03610636 : std_logic is MEM_DATAL_MB3_O(( 7 )); alias N_03610641 : std_logic is MEM_DATAL_MB3_O(( 8 )); alias N_03610337 : std_logic is rsfifo_data_int(0); alias N_03610338 : std_logic is rsfifo_data_int(1); alias N_03610339 : std_logic is rsfifo_data_int(2); alias N_03610340 : std_logic is rsfifo_data_int(3); alias N_03610369 : std_logic is rsfifo_data_int(4); alias N_03610371 : std_logic is rsfifo_data_int(5); alias N_03610373 : std_logic is rsfifo_data_int(6); alias N_03610375 : std_logic is rsfifo_data_int(7); alias N_03610377 : std_logic is rsfifo_data_int(8); alias N_03610379 : std_logic is rsfifo_data_int(9); alias N_03610381 : std_logic is rsfifo_data_int(10); alias N_03610383 : std_logic is rsfifo_data_int(11); alias N_03610385 : std_logic is rsfifo_data_int(12); alias N_03610387 : std_logic is rsfifo_data_int(13); alias N_03610389 : std_logic is rsfifo_data_int(14); alias N_03610391 : std_logic is rsfifo_data_int(15); alias N_03610393 : std_logic is rsfifo_data_int(16); alias N_03610395 : std_logic is rsfifo_data_int(17); -- COMPONENT_DECLARATIONS component BMZ12FPU port( I : in std_logic; T : in std_logic; O : out std_logic; B : inout std_logic ); end component; component CLKCNTLT port( CLKIN : in std_logic; SHUTOFF : in std_logic; CLKOUT : out std_logic ); end component; component DCE32X4 port( CK : in std_logic; DI0 : in std_logic; DI1 : in std_logic; DI2 : in std_logic; DI3 : in std_logic; RAD0 : in std_logic; RAD1 : in std_logic; RAD2 : in std_logic; RAD3 : in std_logic; RAD4 : in std_logic; WAD0 : in std_logic; WAD1 : in std_logic; WAD2 : in std_logic; WAD3 : in std_logic; WAD4 : in std_logic; WPE0 : in std_logic; WPE1 : in std_logic; WREN : in std_logic; DO0 : out std_logic; DO1 : out std_logic; DO2 : out std_logic; DO3 : out std_logic; QDO0 : out std_logic; QDO1 : out std_logic; QDO2 : out std_logic; QDO3 : out std_logic ); end component; component GSR port( GSR : in std_logic ); end component; component IBTPU port( I : in std_logic; O : out std_logic ); end component; component IFS1P3DX port( CD : in std_logic; D : in std_logic; SCLK : in std_logic; SP : in std_logic; Q : out std_logic ); end component; component INV port( A : in std_logic; Z : out std_logic ); end component; component OFS1P3DX port( CD : in std_logic; D : in std_logic; SCLK : in std_logic; SP : in std_logic; Q : out std_logic ); end component; component VHI port( Z : out std_logic ); end component; component VLO port( Z : out std_logic ); end component; component clk_loader port( CLK : in std_logic; CLK_LOAD : in std_logic; M : in std_logic_vector(8 downto 0); N : in std_logic_vector(1 downto 0); RST : in std_logic; T : in std_logic_vector(2 downto 0); clk_test : in std_logic; clk_data : out std_logic; clk_ld : out std_logic; clk_ld_clk : out std_logic ); end component; component com_generator port( CLK : in std_logic; RST : in std_logic; command : in std_logic_vector(3 downto 0); data : in std_logic_vector(31 downto 0); execute : in std_logic; send_triggers : in std_logic; bitstream : out std_logic; busy : out std_logic; send_stream : out std_logic ); end component; component fifo_controller port( CLEAR : in std_logic; CLK : in std_logic; READ : in std_logic; RST : in std_logic; WRITE : in std_logic; EMPTY : out std_logic; FULL : out std_logic; READ_ADDR : out std_logic_vector(4 downto 0); WREN : out std_logic; WRITE_ADDR : out std_logic_vector(4 downto 0) ); end component; component histo_circ port( BASE_ADDRESS : in std_logic_vector(7 downto 0); CLK : in std_logic; LOAD_BASE_ADDRESS : in std_logic; MEMORY_CLEAR : in std_logic; MEM_DATAH_MB2_I : in std_logic_vector(8 downto 0); MEM_DATAH_MB3_I : in std_logic_vector(8 downto 0); MEM_DATAL_MB2_I : in std_logic_vector(8 downto 0); MEM_DATAL_MB3_I : in std_logic_vector(8 downto 0); READ : in std_logic; RST : in std_logic; START_HISTOGRAMMING : in std_logic; STOP_HISTOGRAMMING : in std_logic; channel_A : in std_logic_vector(6 downto 0); channel_B : in std_logic_vector(6 downto 0); chip_A : in std_logic_vector(3 downto 0); chip_B : in std_logic_vector(3 downto 0); empty_A : in std_logic; empty_B : in std_logic; full_A : in std_logic; full_B : in std_logic; BS_MB2 : out std_logic_vector(2 downto 0); BS_MB3 : out std_logic_vector(2 downto 0); BUSY : out std_logic; G_MB2 : out std_logic_vector(1 downto 0); G_MB3 : out std_logic_vector(1 downto 0); MEM2_TRISTATE : out std_logic_vector(3 downto 0); MEM3_TRISTATE : out std_logic_vector(3 downto 0); MEM_ADDR_MB2 : out std_logic_vector(18 downto 0); MEM_ADDR_MB3 : out std_logic_vector(18 downto 0); MEM_DATAH_MB2_O : out std_logic_vector(8 downto 0); MEM_DATAH_MB3_O : out std_logic_vector(8 downto 0); MEM_DATAL_MB2_O : out std_logic_vector(8 downto 0); MEM_DATAL_MB3_O : out std_logic_vector(8 downto 0); SW_MB2 : out std_logic; SW_MB3 : out std_logic; VME_READ_DATA : out std_logic_vector(31 downto 0); clear_fifo_A : out std_logic; clear_fifo_B : out std_logic; read_A : out std_logic; read_B : out std_logic ); end component; component histo_controller port( BUSY_IN : in std_logic; CLK : in std_logic; RST : in std_logic; START : in std_logic; BUSY : out std_logic; SEND_TRIGGERS : out std_logic; STOP_HIST : out std_logic; STRT_HIST : out std_logic; receive_data : out std_logic; reset_resync_fifo : out std_logic ); end component; component module_controller port( BUSY : in std_logic; CLK : in std_logic; MEM_DATAH_MB0_I : in std_logic_vector(8 downto 0); MEM_DATAH_MB1_I : in std_logic_vector(8 downto 0); MEM_DATAL_MB0_I : in std_logic_vector(8 downto 0); MEM_DATAL_MB1_I : in std_logic_vector(8 downto 0); RESYNC_FIFO_DATA : in std_logic_vector(17 downto 0); RST : in std_logic; SIM_MEM_CNT_RST : in std_logic; SIM_MEM_WRITE : in std_logic; START : in std_logic; TV_MEM_CNT_RST : in std_logic; TV_MEM_WRITE : in std_logic; VME_DATA : in std_logic_vector(17 downto 0); BS_MB0 : out std_logic_vector(2 downto 0); BS_MB1 : out std_logic_vector(2 downto 0); DIFFERENCE_FOUND : out std_logic; G_MB0 : out std_logic_vector(1 downto 0); G_MB1 : out std_logic_vector(1 downto 0); LOAD : out std_logic; MEM0_TRISTATE : out std_logic_vector(3 downto 0); MEM1_TRISTATE : out std_logic_vector(3 downto 0); MEM_ADDR_MB0 : out std_logic_vector(18 downto 0); MEM_ADDR_MB1 : out std_logic_vector(18 downto 0); MEM_DATAH_MB0_O : out std_logic_vector(8 downto 0); MEM_DATAH_MB1_O : out std_logic_vector(8 downto 0); MEM_DATAL_MB0_O : out std_logic_vector(8 downto 0); MEM_DATAL_MB1_O : out std_logic_vector(8 downto 0); OUTFIFO_DATA : out std_logic_vector(17 downto 0); READ_FROM_FIFO : out std_logic; RECEIVE_DATA : out std_logic; RESET_FIFO : out std_logic; RESYNC_FIFO_RST : out std_logic; RUNNING : out std_logic; SEND_FIFO : out std_logic; SW_MB0 : out std_logic; SW_MB1 : out std_logic ); end component; component outfifo_contr port( clk : in std_logic; cmd_stream : in std_logic; efb : in std_logic; ffb : in std_logic; mem_data : in std_logic_vector(17 downto 0); reset_fifo_int : in std_logic; rst : in std_logic; send_fifo_int : in std_logic; send_stream : in std_logic; write_mem_data_to_fifo : in std_logic; busy_int : out std_logic; data : out std_logic_vector(17 downto 0); mrsb : out std_logic; oenb : out std_logic; renb : out std_logic; rtb : out std_logic; wenb : out std_logic ); end component; component resync_fifo_contr port( clk : in std_logic; efb : in std_logic; ffb : in std_logic; read : in std_logic; read_TV_data : in std_logic; receive_TV_data : in std_logic; receive_data : in std_logic; reset_fifo : in std_logic; reset_fifo_2 : in std_logic; retransmit : in std_logic; rst : in std_logic; mrsb : out std_logic; oenb : out std_logic; renb : out std_logic; rtb : out std_logic; vme_data : out std_logic_vector(17 downto 0); wenb : out std_logic ); end component; component serialtoparallel port( clk : in std_logic; rst : in std_logic; serial_data : in std_logic; bc : out std_logic_vector(7 downto 0); channel : out std_logic_vector(6 downto 0); chip : out std_logic_vector(3 downto 0); l1t : out std_logic_vector(3 downto 0); write : out std_logic ); end component; component test_connector port( CLK : in std_logic; LAST_COMMAND : in std_logic_vector(4 downto 0); RST : in std_logic; RUNNING : in std_logic; VALID_VME_ACCESS : in std_logic; t0 : in std_logic; t1 : in std_logic; t2 : in std_logic; t3 : in std_logic; t4 : in std_logic; t5 : in std_logic; t6 : in std_logic; t7 : in std_logic; t8 : in std_logic; t9 : in std_logic; LED : out std_logic_vector(8 downto 0); TC : out std_logic_vector(19 downto 0) ); end component; component vme_decoder port( BOARD_ADDR : in std_logic_vector(7 downto 0); CLK : in std_logic; DIFFERENCE_FOUND : in std_logic; HISTOGRAMMING_BUSY : in std_logic; HISTO_BLOCK_BUSY : in std_logic; HISTO_MEM_DATA_IN : in std_logic_vector(31 downto 0); LADDR : in std_logic_vector(31 downto 1); RESYNC_FIFO_DATA : in std_logic_vector(17 downto 0); RST : in std_logic; SVIC_CS : in std_logic_vector(5 downto 0); SVIC_DBE : in std_logic_vector(3 downto 0); SVIC_LDEN_N : in std_logic; SVIC_LDS : in std_logic; SVIC_PREN_N : in std_logic; SVIC_R_W : in std_logic; SVIC_STROBE : in std_logic; SVIC_SWDEN_N : in std_logic; TV_RUNNING : in std_logic; VCOMP : in std_logic_vector(3 downto 0); BASE_ADDRESS : out std_logic_vector(7 downto 0); CLK_LOAD : out std_logic; CLK_M : out std_logic_vector(8 downto 0); CLK_N : out std_logic_vector(1 downto 0); CLK_T : out std_logic_vector(2 downto 0); COMMAND : out std_logic_vector(3 downto 0); COMMAND_DATA : out std_logic_vector(31 downto 0); EXECUTE_COMMAND : out std_logic; HISTO_MEM_CLEAR : out std_logic; HISTO_MEM_READ : out std_logic; LAST_COMMAND : out std_logic_vector(4 downto 0); LOAD_BASE_ADDRESS : out std_logic; RSFIFO_READ : out std_logic; RSFIFO_RETRANSMIT : out std_logic; SIM_MEM_CNT_RST : out std_logic; SIM_MEM_WRITE : out std_logic; START_HISTOGRAMMING : out std_logic; START_SENDING_TV : out std_logic; SVIC_LACK_N : out std_logic; SVIC_LIRQ : out std_logic; SVIC_REGION : out std_logic_vector(3 downto 0); TV_MEM_CNT_RST : out std_logic; TV_MEM_WRITE : out std_logic; TV_OR_SIM_DATA : out std_logic_vector(17 downto 0); VALID_VME_ACCESS : out std_logic; VME_XCVR_LDS : out std_logic; VME_XCVR_MWB_N : out std_logic; VME_XCVR_STROBE_N : out std_logic; LDATA : inout std_logic_vector(31 downto 0) ); end component; -- INLINE CONFIGURATIONS -- for I_03610059 : com_generator use entity hdl.com_generator(structure); -- for I_03610261 : resync_fifo_contr use entity hdl.resync_fifo_contr(structure); -- for I_03610463 : histo_controller use entity hdl.histo_controller(structure); -- for I_03612146 : DCE32X4 use entity hdl.DCE32X4(structure); -- for I_03612147 : VHI use entity hdl.VHI(structure); -- for I_03612168 : DCE32X4 use entity hdl.DCE32X4(structure); -- for I_03612169 : DCE32X4 use entity hdl.DCE32X4(structure); -- for I_03612170 : VHI use entity hdl.VHI(structure); -- for I_03612171 : VHI use entity hdl.VHI(structure); -- for I_03612174 : VHI use entity hdl.VHI(structure); -- for I_03612211 : fifo_controller use entity hdl.fifo_controller(structure); -- for I_03612220 : fifo_controller use entity hdl.fifo_controller(structure); -- for I_03612229 : DCE32X4 use entity hdl.DCE32X4(structure); -- for I_03612230 : DCE32X4 use entity hdl.DCE32X4(structure); -- for I_03612231 : DCE32X4 use entity hdl.DCE32X4(structure); -- for I_03612232 : VHI use entity hdl.VHI(structure); -- for I_03612233 : VHI use entity hdl.VHI(structure); -- for I_03612234 : VHI use entity hdl.VHI(structure); -- for I_03612238 : VHI use entity hdl.VHI(structure); -- for I_0362531 : VLO use entity hdl.VLO(structure); -- for I_0362532 : CLKCNTLT use entity hdl.CLKCNTLT(structure); -- for I_0362534 : IBTPU use entity work.IBTPU(black_box); -- for I_0362535 : GSR use entity work.GSR(black_box); -- for I_036307 : histo_circ use entity hdl.histo_circ(structure); -- for I_03643 : module_controller use entity hdl.module_controller(structure); -- for I_0364526 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0364527 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364528 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0364529 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364530 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0364531 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364532 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0364533 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364534 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0364535 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364536 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0364537 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364538 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0364539 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0364540 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364541 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0364542 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364543 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0364544 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364545 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0364546 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364547 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0364548 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364549 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0364550 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364551 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0364552 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364553 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0364554 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364555 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0364556 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364557 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0364558 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364559 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0364560 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364561 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0364562 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364563 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0364564 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364565 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0364566 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364567 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0364568 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364569 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0364570 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364571 : VHI use entity hdl.VHI(structure); -- for I_0364576 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364577 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0364578 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364579 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0364580 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364581 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0364582 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364583 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0364584 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364585 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0364586 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364587 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0364588 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364589 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0364590 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364591 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0364592 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364593 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0364594 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364595 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0364596 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364597 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0364598 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364599 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0364600 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364601 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0364602 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364603 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0364604 : VHI use entity hdl.VHI(structure); -- for I_0364605 : VHI use entity hdl.VHI(structure); -- for I_0364609 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0364610 : VHI use entity hdl.VHI(structure); -- for I_0364611 : VHI use entity hdl.VHI(structure); -- for I_0364615 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0364616 : VHI use entity hdl.VHI(structure); -- for I_0364617 : VHI use entity hdl.VHI(structure); -- for I_0364621 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0364622 : VHI use entity hdl.VHI(structure); -- for I_0364623 : VHI use entity hdl.VHI(structure); -- for I_0364627 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0364628 : VHI use entity hdl.VHI(structure); -- for I_0364629 : VHI use entity hdl.VHI(structure); -- for I_0364633 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0364634 : VHI use entity hdl.VHI(structure); -- for I_0364636 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0364637 : VHI use entity hdl.VHI(structure); -- for I_0364638 : VHI use entity hdl.VHI(structure); -- for I_0364642 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0364643 : VHI use entity hdl.VHI(structure); -- for I_0364644 : VHI use entity hdl.VHI(structure); -- for I_0364649 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0364650 : VHI use entity hdl.VHI(structure); -- for I_0364651 : VHI use entity hdl.VHI(structure); -- for I_0364655 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0364656 : VHI use entity hdl.VHI(structure); -- for I_0364657 : VHI use entity hdl.VHI(structure); -- for I_0364661 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0364662 : VHI use entity hdl.VHI(structure); -- for I_0364663 : VHI use entity hdl.VHI(structure); -- for I_0364670 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0364671 : VHI use entity hdl.VHI(structure); -- for I_0364672 : VHI use entity hdl.VHI(structure); -- for I_0364676 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0364677 : VHI use entity hdl.VHI(structure); -- for I_0364678 : VHI use entity hdl.VHI(structure); -- for I_0364682 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0364683 : VHI use entity hdl.VHI(structure); -- for I_0364684 : VHI use entity hdl.VHI(structure); -- for I_0364688 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0364689 : VHI use entity hdl.VHI(structure); -- for I_0364690 : VHI use entity hdl.VHI(structure); -- for I_0364694 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0364695 : VHI use entity hdl.VHI(structure); -- for I_0364696 : VHI use entity hdl.VHI(structure); -- for I_0364699 : VHI use entity hdl.VHI(structure); -- for I_0364703 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0364704 : VHI use entity hdl.VHI(structure); -- for I_0364705 : VHI use entity hdl.VHI(structure); -- for I_0364709 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0364710 : VHI use entity hdl.VHI(structure); -- for I_0364711 : VHI use entity hdl.VHI(structure); -- for I_0364715 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0364716 : VHI use entity hdl.VHI(structure); -- for I_0364717 : VHI use entity hdl.VHI(structure); -- for I_0364722 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0364723 : VHI use entity hdl.VHI(structure); -- for I_0364724 : VHI use entity hdl.VHI(structure); -- for I_0364728 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0364729 : VHI use entity hdl.VHI(structure); -- for I_0364730 : VHI use entity hdl.VHI(structure); -- for I_0364731 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0364732 : VHI use entity hdl.VHI(structure); -- for I_0364733 : VHI use entity hdl.VHI(structure); -- for I_0364737 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0364738 : VHI use entity hdl.VHI(structure); -- for I_0364739 : VHI use entity hdl.VHI(structure); -- for I_0364743 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0364744 : VHI use entity hdl.VHI(structure); -- for I_0364745 : VHI use entity hdl.VHI(structure); -- for I_0364749 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0364750 : VHI use entity hdl.VHI(structure); -- for I_0364751 : VHI use entity hdl.VHI(structure); -- for I_0364755 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0364756 : VHI use entity hdl.VHI(structure); -- for I_0364757 : VHI use entity hdl.VHI(structure); -- for I_0364761 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0364762 : VHI use entity hdl.VHI(structure); -- for I_0364764 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0364765 : VHI use entity hdl.VHI(structure); -- for I_0364766 : VHI use entity hdl.VHI(structure); -- for I_0364770 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0364771 : VHI use entity hdl.VHI(structure); -- for I_0364772 : VHI use entity hdl.VHI(structure); -- for I_0364776 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0364777 : VHI use entity hdl.VHI(structure); -- for I_0364778 : VHI use entity hdl.VHI(structure); -- for I_0364782 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0364783 : VHI use entity hdl.VHI(structure); -- for I_0364784 : VHI use entity hdl.VHI(structure); -- for I_0364788 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0364789 : VHI use entity hdl.VHI(structure); -- for I_0364790 : VHI use entity hdl.VHI(structure); -- for I_0364795 : VHI use entity hdl.VHI(structure); -- for I_0364796 : VHI use entity hdl.VHI(structure); -- for I_0364797 : VHI use entity hdl.VHI(structure); -- for I_0364798 : VHI use entity hdl.VHI(structure); -- for I_0364799 : VHI use entity hdl.VHI(structure); -- for I_0364800 : VHI use entity hdl.VHI(structure); -- for I_0364801 : VHI use entity hdl.VHI(structure); -- for I_0364802 : VHI use entity hdl.VHI(structure); -- for I_0364803 : VHI use entity hdl.VHI(structure); -- for I_0364804 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0364805 : VHI use entity hdl.VHI(structure); -- for I_0364806 : VHI use entity hdl.VHI(structure); -- for I_0364810 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0364811 : VHI use entity hdl.VHI(structure); -- for I_0364812 : VHI use entity hdl.VHI(structure); -- for I_0364816 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0364817 : VHI use entity hdl.VHI(structure); -- for I_0364818 : VHI use entity hdl.VHI(structure); -- for I_0364822 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0364823 : VHI use entity hdl.VHI(structure); -- for I_0364824 : VHI use entity hdl.VHI(structure); -- for I_0364831 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364833 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364834 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364835 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364836 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364837 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364850 : VHI use entity hdl.VHI(structure); -- for I_0364851 : VHI use entity hdl.VHI(structure); -- for I_0364852 : VHI use entity hdl.VHI(structure); -- for I_0364853 : VHI use entity hdl.VHI(structure); -- for I_0364854 : VHI use entity hdl.VHI(structure); -- for I_0364855 : VHI use entity hdl.VHI(structure); -- for I_0364856 : VHI use entity hdl.VHI(structure); -- for I_0364857 : VHI use entity hdl.VHI(structure); -- for I_0364858 : VHI use entity hdl.VHI(structure); -- for I_0364859 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364861 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364862 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364863 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364864 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364865 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364877 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364879 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364880 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364881 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364882 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0364883 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_036512 : test_connector use entity hdl.test_connector(structure); -- for I_0365509 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365511 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365512 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365513 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365514 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365515 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365527 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365529 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365530 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365531 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365532 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365533 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365545 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365547 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365548 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365549 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365550 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365551 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365564 : VHI use entity hdl.VHI(structure); -- for I_0365565 : VHI use entity hdl.VHI(structure); -- for I_0365566 : VHI use entity hdl.VHI(structure); -- for I_0365567 : VHI use entity hdl.VHI(structure); -- for I_0365568 : VHI use entity hdl.VHI(structure); -- for I_0365569 : VHI use entity hdl.VHI(structure); -- for I_0365570 : VHI use entity hdl.VHI(structure); -- for I_0365571 : VHI use entity hdl.VHI(structure); -- for I_0365572 : VHI use entity hdl.VHI(structure); -- for I_0365573 : VHI use entity hdl.VHI(structure); -- for I_0365574 : VHI use entity hdl.VHI(structure); -- for I_0365575 : VHI use entity hdl.VHI(structure); -- for I_0365576 : VHI use entity hdl.VHI(structure); -- for I_0365577 : VHI use entity hdl.VHI(structure); -- for I_0365578 : VHI use entity hdl.VHI(structure); -- for I_0365579 : VHI use entity hdl.VHI(structure); -- for I_0365580 : VHI use entity hdl.VHI(structure); -- for I_0365581 : VHI use entity hdl.VHI(structure); -- for I_0365584 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365586 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365587 : VHI use entity hdl.VHI(structure); -- for I_0365589 : INV use entity hdl.INV(structure); -- for I_0365591 : VHI use entity hdl.VHI(structure); -- for I_0365592 : VHI use entity hdl.VHI(structure); -- for I_0365593 : VHI use entity hdl.VHI(structure); -- for I_0365594 : VHI use entity hdl.VHI(structure); -- for I_0365595 : VHI use entity hdl.VHI(structure); -- for I_0365596 : VHI use entity hdl.VHI(structure); -- for I_0365597 : VHI use entity hdl.VHI(structure); -- for I_0365598 : VHI use entity hdl.VHI(structure); -- for I_0365599 : VHI use entity hdl.VHI(structure); -- for I_0365600 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365603 : VHI use entity hdl.VHI(structure); -- for I_0365608 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365610 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365611 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365612 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365613 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365614 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365625 : VHI use entity hdl.VHI(structure); -- for I_0365626 : VHI use entity hdl.VHI(structure); -- for I_0365627 : VHI use entity hdl.VHI(structure); -- for I_0365628 : VHI use entity hdl.VHI(structure); -- for I_0365629 : VHI use entity hdl.VHI(structure); -- for I_0365630 : VHI use entity hdl.VHI(structure); -- for I_0365631 : VHI use entity hdl.VHI(structure); -- for I_0365632 : VHI use entity hdl.VHI(structure); -- for I_0365633 : VHI use entity hdl.VHI(structure); -- for I_0365634 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365635 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365636 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365637 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365638 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365650 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365652 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365653 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365654 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365655 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365656 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365665 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365666 : VHI use entity hdl.VHI(structure); -- for I_0365668 : INV use entity hdl.INV(structure); -- for I_0365669 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365672 : VHI use entity hdl.VHI(structure); -- for I_03658 : clk_loader use entity hdl.clk_loader(structure); -- for I_0365876 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365877 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0365879 : VHI use entity hdl.VHI(structure); -- for I_0365880 : VHI use entity hdl.VHI(structure); -- for I_0366082 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0366083 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0366084 : VHI use entity hdl.VHI(structure); -- for I_0366085 : VHI use entity hdl.VHI(structure); -- for I_0366086 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0366087 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0366088 : VHI use entity hdl.VHI(structure); -- for I_0366089 : VHI use entity hdl.VHI(structure); -- for I_0366574 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0366575 : VHI use entity hdl.VHI(structure); -- for I_0366578 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0366580 : VHI use entity hdl.VHI(structure); -- for I_0366581 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0366582 : VHI use entity hdl.VHI(structure); -- for I_0366583 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0366584 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0366585 : VHI use entity hdl.VHI(structure); -- for I_0366586 : VHI use entity hdl.VHI(structure); -- for I_0366587 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0366792 : VHI use entity hdl.VHI(structure); -- for I_0366793 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0366995 : VHI use entity hdl.VHI(structure); -- for I_0367197 : INV use entity hdl.INV(structure); -- for I_0367198 : INV use entity hdl.INV(structure); -- for I_0367463 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367465 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367466 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367467 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367468 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367469 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367481 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367483 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367484 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367485 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367486 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367487 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367499 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367501 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367502 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367503 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367504 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367505 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367518 : VHI use entity hdl.VHI(structure); -- for I_0367519 : VHI use entity hdl.VHI(structure); -- for I_0367520 : VHI use entity hdl.VHI(structure); -- for I_0367521 : VHI use entity hdl.VHI(structure); -- for I_0367522 : VHI use entity hdl.VHI(structure); -- for I_0367523 : VHI use entity hdl.VHI(structure); -- for I_0367524 : VHI use entity hdl.VHI(structure); -- for I_0367525 : VHI use entity hdl.VHI(structure); -- for I_0367526 : VHI use entity hdl.VHI(structure); -- for I_0367527 : VHI use entity hdl.VHI(structure); -- for I_0367528 : VHI use entity hdl.VHI(structure); -- for I_0367529 : VHI use entity hdl.VHI(structure); -- for I_0367530 : VHI use entity hdl.VHI(structure); -- for I_0367531 : VHI use entity hdl.VHI(structure); -- for I_0367532 : VHI use entity hdl.VHI(structure); -- for I_0367533 : VHI use entity hdl.VHI(structure); -- for I_0367534 : VHI use entity hdl.VHI(structure); -- for I_0367535 : VHI use entity hdl.VHI(structure); -- for I_0367536 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367537 : VHI use entity hdl.VHI(structure); -- for I_0367539 : INV use entity hdl.INV(structure); -- for I_0367540 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367543 : VHI use entity hdl.VHI(structure); -- for I_0367545 : INV use entity hdl.INV(structure); -- for I_0367546 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367549 : VHI use entity hdl.VHI(structure); -- for I_0367562 : VHI use entity hdl.VHI(structure); -- for I_0367563 : VHI use entity hdl.VHI(structure); -- for I_0367564 : VHI use entity hdl.VHI(structure); -- for I_0367565 : VHI use entity hdl.VHI(structure); -- for I_0367566 : VHI use entity hdl.VHI(structure); -- for I_0367567 : VHI use entity hdl.VHI(structure); -- for I_0367568 : VHI use entity hdl.VHI(structure); -- for I_0367569 : VHI use entity hdl.VHI(structure); -- for I_0367570 : VHI use entity hdl.VHI(structure); -- for I_0367571 : VHI use entity hdl.VHI(structure); -- for I_0367572 : VHI use entity hdl.VHI(structure); -- for I_0367573 : VHI use entity hdl.VHI(structure); -- for I_0367574 : VHI use entity hdl.VHI(structure); -- for I_0367575 : VHI use entity hdl.VHI(structure); -- for I_0367576 : VHI use entity hdl.VHI(structure); -- for I_0367577 : VHI use entity hdl.VHI(structure); -- for I_0367578 : VHI use entity hdl.VHI(structure); -- for I_0367579 : VHI use entity hdl.VHI(structure); -- for I_0367580 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367581 : VHI use entity hdl.VHI(structure); -- for I_0367589 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367591 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367592 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367593 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367594 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367595 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367607 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367609 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367610 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367611 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367612 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367613 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367615 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367617 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367618 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367619 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367620 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367621 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367833 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367834 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367836 : VHI use entity hdl.VHI(structure); -- for I_0367837 : VHI use entity hdl.VHI(structure); -- for I_0367839 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367840 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367842 : VHI use entity hdl.VHI(structure); -- for I_0367843 : VHI use entity hdl.VHI(structure); -- for I_0367844 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367845 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0367846 : VHI use entity hdl.VHI(structure); -- for I_0367847 : VHI use entity hdl.VHI(structure); -- for I_0368759 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0368760 : VHI use entity hdl.VHI(structure); -- for I_0368763 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0368764 : VHI use entity hdl.VHI(structure); -- for I_0368767 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0368768 : VHI use entity hdl.VHI(structure); -- for I_0368771 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0368772 : VHI use entity hdl.VHI(structure); -- for I_0368775 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0368776 : VHI use entity hdl.VHI(structure); -- for I_0368779 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0368780 : VHI use entity hdl.VHI(structure); -- for I_0368783 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0368784 : VHI use entity hdl.VHI(structure); -- for I_0368787 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0368788 : VHI use entity hdl.VHI(structure); -- for I_0368791 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0368792 : VHI use entity hdl.VHI(structure); -- for I_0368795 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0368796 : VHI use entity hdl.VHI(structure); -- for I_0368799 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0368800 : VHI use entity hdl.VHI(structure); -- for I_0368803 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0368804 : VHI use entity hdl.VHI(structure); -- for I_0368806 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0368808 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0368809 : VHI use entity hdl.VHI(structure); -- for I_0368812 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0368813 : VHI use entity hdl.VHI(structure); -- for I_0368817 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0368818 : VHI use entity hdl.VHI(structure); -- for I_0368821 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0368822 : VHI use entity hdl.VHI(structure); -- for I_0368827 : INV use entity hdl.INV(structure); -- for I_0368828 : INV use entity hdl.INV(structure); -- for I_0368829 : INV use entity hdl.INV(structure); -- for I_0368830 : INV use entity hdl.INV(structure); -- for I_0368835 : INV use entity hdl.INV(structure); -- for I_0368836 : INV use entity hdl.INV(structure); -- for I_0368837 : INV use entity hdl.INV(structure); -- for I_0368838 : INV use entity hdl.INV(structure); -- for I_0368839 : INV use entity hdl.INV(structure); -- for I_0368840 : INV use entity hdl.INV(structure); -- for I_0368841 : INV use entity hdl.INV(structure); -- for I_0368842 : INV use entity hdl.INV(structure); -- for I_0368843 : INV use entity hdl.INV(structure); -- for I_0368844 : INV use entity hdl.INV(structure); -- for I_0368845 : INV use entity hdl.INV(structure); -- for I_0368846 : INV use entity hdl.INV(structure); -- for I_0368850 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0368851 : VHI use entity hdl.VHI(structure); -- for I_0368853 : VHI use entity hdl.VHI(structure); -- for I_0368854 : INV use entity hdl.INV(structure); -- for I_0368855 : INV use entity hdl.INV(structure); -- for I_0368869 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0368870 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0368872 : VHI use entity hdl.VHI(structure); -- for I_0368873 : VHI use entity hdl.VHI(structure); -- for I_0368874 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0368875 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0368876 : VHI use entity hdl.VHI(structure); -- for I_0368877 : VHI use entity hdl.VHI(structure); -- for I_0368878 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0368879 : VHI use entity hdl.VHI(structure); -- for I_0368880 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0368883 : VHI use entity hdl.VHI(structure); -- for I_0368884 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0368886 : VHI use entity hdl.VHI(structure); -- for I_0368887 : INV use entity hdl.INV(structure); -- for I_0368888 : INV use entity hdl.INV(structure); -- for I_0369090 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0369091 : VHI use entity hdl.VHI(structure); -- for I_0369092 : VHI use entity hdl.VHI(structure); -- for I_0369096 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0369097 : VHI use entity hdl.VHI(structure); -- for I_0369098 : VHI use entity hdl.VHI(structure); -- for I_0369102 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0369103 : VHI use entity hdl.VHI(structure); -- for I_0369104 : VHI use entity hdl.VHI(structure); -- for I_0369108 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0369109 : VHI use entity hdl.VHI(structure); -- for I_0369110 : VHI use entity hdl.VHI(structure); -- for I_0369114 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0369115 : VHI use entity hdl.VHI(structure); -- for I_0369116 : VHI use entity hdl.VHI(structure); -- for I_0369120 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0369121 : VHI use entity hdl.VHI(structure); -- for I_0369122 : VHI use entity hdl.VHI(structure); -- for I_0369126 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0369127 : VHI use entity hdl.VHI(structure); -- for I_0369128 : VHI use entity hdl.VHI(structure); -- for I_0369132 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0369133 : VHI use entity hdl.VHI(structure); -- for I_0369134 : VHI use entity hdl.VHI(structure); -- for I_0369138 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0369139 : VHI use entity hdl.VHI(structure); -- for I_0369140 : VHI use entity hdl.VHI(structure); -- for I_0369145 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0369146 : VHI use entity hdl.VHI(structure); -- for I_0369147 : VHI use entity hdl.VHI(structure); -- for I_0369151 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0369152 : VHI use entity hdl.VHI(structure); -- for I_0369153 : VHI use entity hdl.VHI(structure); -- for I_0369157 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0369158 : VHI use entity hdl.VHI(structure); -- for I_0369159 : VHI use entity hdl.VHI(structure); -- for I_0369163 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0369164 : VHI use entity hdl.VHI(structure); -- for I_0369165 : VHI use entity hdl.VHI(structure); -- for I_0369169 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0369170 : VHI use entity hdl.VHI(structure); -- for I_0369171 : VHI use entity hdl.VHI(structure); -- for I_0369175 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0369176 : VHI use entity hdl.VHI(structure); -- for I_0369177 : VHI use entity hdl.VHI(structure); -- for I_0369181 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0369182 : VHI use entity hdl.VHI(structure); -- for I_0369183 : VHI use entity hdl.VHI(structure); -- for I_0369187 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0369188 : VHI use entity hdl.VHI(structure); -- for I_0369189 : VHI use entity hdl.VHI(structure); -- for I_0369193 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0369194 : VHI use entity hdl.VHI(structure); -- for I_0369195 : VHI use entity hdl.VHI(structure); -- for I_0369200 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0369201 : VHI use entity hdl.VHI(structure); -- for I_0369202 : VHI use entity hdl.VHI(structure); -- for I_0369206 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0369207 : VHI use entity hdl.VHI(structure); -- for I_0369208 : VHI use entity hdl.VHI(structure); -- for I_0369212 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0369213 : VHI use entity hdl.VHI(structure); -- for I_0369214 : VHI use entity hdl.VHI(structure); -- for I_0369218 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0369219 : VHI use entity hdl.VHI(structure); -- for I_0369220 : VHI use entity hdl.VHI(structure); -- for I_0369224 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0369225 : VHI use entity hdl.VHI(structure); -- for I_0369226 : VHI use entity hdl.VHI(structure); -- for I_0369230 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0369231 : VHI use entity hdl.VHI(structure); -- for I_0369232 : VHI use entity hdl.VHI(structure); -- for I_0369236 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0369237 : VHI use entity hdl.VHI(structure); -- for I_0369238 : VHI use entity hdl.VHI(structure); -- for I_0369242 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0369243 : VHI use entity hdl.VHI(structure); -- for I_0369244 : VHI use entity hdl.VHI(structure); -- for I_0369248 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0369249 : VHI use entity hdl.VHI(structure); -- for I_0369250 : VHI use entity hdl.VHI(structure); -- for I_0369255 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0369256 : VHI use entity hdl.VHI(structure); -- for I_0369257 : VHI use entity hdl.VHI(structure); -- for I_0369261 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0369262 : VHI use entity hdl.VHI(structure); -- for I_0369263 : VHI use entity hdl.VHI(structure); -- for I_0369267 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0369268 : VHI use entity hdl.VHI(structure); -- for I_0369269 : VHI use entity hdl.VHI(structure); -- for I_0369273 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0369274 : VHI use entity hdl.VHI(structure); -- for I_0369275 : VHI use entity hdl.VHI(structure); -- for I_0369279 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0369280 : VHI use entity hdl.VHI(structure); -- for I_0369281 : VHI use entity hdl.VHI(structure); -- for I_0369285 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0369286 : VHI use entity hdl.VHI(structure); -- for I_0369287 : VHI use entity hdl.VHI(structure); -- for I_0369291 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0369292 : VHI use entity hdl.VHI(structure); -- for I_0369293 : VHI use entity hdl.VHI(structure); -- for I_0369297 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0369298 : VHI use entity hdl.VHI(structure); -- for I_0369299 : VHI use entity hdl.VHI(structure); -- for I_0369303 : BMZ12FPU use entity hdl.BMZ12FPU(structure); -- for I_0369304 : VHI use entity hdl.VHI(structure); -- for I_0369305 : VHI use entity hdl.VHI(structure); -- for I_0369310 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0369311 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0369312 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0369313 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0369314 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0369315 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0369316 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0369317 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0369318 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0369319 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0369320 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0369321 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0369322 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0369323 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0369324 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0369325 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0369326 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0369327 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0369328 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0369329 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0369330 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0369331 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0369332 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0369333 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0369334 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0369335 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0369336 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0369337 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0369338 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0369339 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0369340 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0369341 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0369342 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0369343 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0369344 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0369345 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0369346 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0369347 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0369348 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0369349 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0369350 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0369351 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0369352 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0369353 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0369354 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0369355 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0369356 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0369357 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0369358 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0369359 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0369360 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0369361 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0369362 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0369363 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0369364 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0369365 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0369366 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0369367 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0369368 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0369369 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0369370 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0369371 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0369372 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0369373 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0369374 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0369375 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0369376 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0369377 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0369378 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0369379 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_0369380 : OFS1P3DX use entity hdl.OFS1P3DX(structure); -- for I_0369381 : IFS1P3DX use entity hdl.IFS1P3DX(structure); -- for I_03695 : vme_decoder use entity hdl.vme_decoder(structure); -- for I_0369642 : serialtoparallel use entity hdl.serialtoparallel(structure); -- for I_0369652 : serialtoparallel use entity hdl.serialtoparallel(structure); -- for I_0369857 : outfifo_contr use entity hdl.outfifo_contr(structure); begin -- CONCURRENT SIGNAL ASSIGNMENTS BS_MB0 <= local_BS_MB0; BS_MB1 <= local_BS_MB1; BS_MB2 <= local_BS_MB2; BS_MB3 <= local_BS_MB3; CLEAR_OUT <= local_CLEAR_OUT; CLK_DATA <= local_CLK_DATA; CLK_LD <= local_CLK_LD; CLK_LD_CLK <= local_CLK_LD_CLK; CS_OUT <= local_CS_OUT; G_MB0 <= local_G_MB0; G_MB1 <= local_G_MB1; G_MB2 <= local_G_MB2; G_MB3 <= local_G_MB3; LED <= local_LED; LEMO1 <= local_LEMO1; LEMO2 <= local_LEMO2; LEMO3 <= local_LEMO3; MEM_ADDR_MB0 <= local_MEM_ADDR_MB0; MEM_ADDR_MB1 <= local_MEM_ADDR_MB1; MEM_ADDR_MB2 <= local_MEM_ADDR_MB2; MEM_ADDR_MB3 <= local_MEM_ADDR_MB3; OUTFIFO_DATA <= local_OUTFIFO_DATA; OUTFIFO_MRSB <= local_OUTFIFO_MRSB; OUTFIFO_OENB <= local_OUTFIFO_OENB; OUTFIFO_RENB <= local_OUTFIFO_RENB; OUTFIFO_RTB <= local_OUTFIFO_RTB; OUTFIFO_WENB <= local_OUTFIFO_WENB; RSFIFO_MRSB <= local_RSFIFO_MRSB; RSFIFO_OENB <= local_RSFIFO_OENB; RSFIFO_RENB <= local_RSFIFO_RENB; RSFIFO_RTB <= local_RSFIFO_RTB; RSFIFO_WENB <= local_RSFIFO_WENB; SE3_MB0 <= local_SE3_MB0; SE3_MB1 <= local_SE3_MB1; SE3_MB2 <= local_SE3_MB2; SE3_MB3 <= local_SE3_MB3; SLOW_CLK_OUT <= local_SLOW_CLK_OUT; SPARE_OUT1 <= local_SPARE_OUT1; SPARE_OUT2 <= local_SPARE_OUT2; SVIC_LACK_N <= local_SVIC_LACK_N; SVIC_LIRQ <= local_SVIC_LIRQ; SVIC_REGION <= local_SVIC_REGION; SW_MB0 <= local_SW_MB0; SW_MB1 <= local_SW_MB1; SW_MB2 <= local_SW_MB2; SW_MB3 <= local_SW_MB3; S_DATA_OUT <= local_S_DATA_OUT; TC <= local_TC; VME_XCVR_LDS <= local_VME_XCVR_LDS; VME_XCVR_MWB_N <= local_VME_XCVR_MWB_N; VME_XCVR_STROBE_N <= local_VME_XCVR_STROBE_N; -- COMPONENT INSTANTIATIONS I_03610059 : com_generator port map( CLK => CLK, RST => RST, bitstream => N_03613476, busy => N_03613481, command(3 downto 0) => N_03615276(3 downto 0), data(31 downto 0) => N_03614456(31 downto 0), execute => N_03613484, send_stream => N_03613485, send_triggers => N_03613952 ); I_03610261 : resync_fifo_contr port map( clk => CLK, efb => rsfifo_efb_int, ffb => rsfifo_ffb_int, mrsb => rsfifo_mrsb_int, oenb => rsfifo_oenb_int, read => N_03614454, read_TV_data => read_TV_data, receive_TV_data => receive_TV_data, receive_data => N_03613726, renb => rsfifo_renb_int, reset_fifo => N_03613727, reset_fifo_2 => reset_resync_fifo, retransmit => N_03614453, rst => RST, rtb => rsfifo_rtb_int, vme_data(17 downto 0) => N_03613741(17 downto 0), wenb => rsfifo_wenb_int ); I_03610463 : histo_controller port map( BUSY => N_03613950, BUSY_IN => N_03613481, CLK => CLK, RST => RST, SEND_TRIGGERS => N_03613952, START => N_03614240, STOP_HIST => N_03613048, STRT_HIST => N_03613047, receive_data => N_03613726, reset_resync_fifo => N_03613727 ); I_03612146 : DCE32X4 port map( CK => CLK, DI0 => DI_A(0), DI1 => DI_A(1), DI2 => DI_A(2), DI3 => DI_A(3), DO0 => N_03617237, DO1 => N_03617240, DO2 => N_03617241, DO3 => N_03617242, QDO0 => QDO_A(0), QDO1 => QDO_A(1), QDO2 => QDO_A(2), QDO3 => QDO_A(3), RAD0 => READ_ADDR_A(0), RAD1 => READ_ADDR_A(1), RAD2 => READ_ADDR_A(2), RAD3 => READ_ADDR_A(3), RAD4 => READ_ADDR_A(4), WAD0 => WRITE_ADDR_A(0), WAD1 => WRITE_ADDR_A(1), WAD2 => WRITE_ADDR_A(2), WAD3 => WRITE_ADDR_A(3), WAD4 => WRITE_ADDR_A(4), WPE0 => N_03617239, WPE1 => N_03617239, WREN => wren_A ); I_03612147 : VHI port map( Z => N_03617239 ); I_03612168 : DCE32X4 port map( CK => CLK, DI0 => DI_A(4), DI1 => DI_A(5), DI2 => DI_A(6), DI3 => DI_A(7), DO0 => N_03617258, DO1 => N_03617259, DO2 => N_03617260, DO3 => N_03617261, QDO0 => QDO_A(4), QDO1 => QDO_A(5), QDO2 => QDO_A(6), QDO3 => QDO_A(7), RAD0 => READ_ADDR_A(0), RAD1 => READ_ADDR_A(1), RAD2 => READ_ADDR_A(2), RAD3 => READ_ADDR_A(3), RAD4 => READ_ADDR_A(4), WAD0 => WRITE_ADDR_A(0), WAD1 => WRITE_ADDR_A(1), WAD2 => WRITE_ADDR_A(2), WAD3 => WRITE_ADDR_A(3), WAD4 => WRITE_ADDR_A(4), WPE0 => N_03617282, WPE1 => N_03617282, WREN => wren_A ); I_03612169 : DCE32X4 port map( CK => CLK, DI0 => DI_A(8), DI1 => DI_A(9), DI2 => DI_A(10), DI3 => N_03617273, DO0 => N_03617262, DO1 => N_03617263, DO2 => N_03617264, DO3 => N_03617265, QDO0 => QDO_A(8), QDO1 => QDO_A(9), QDO2 => QDO_A(10), QDO3 => N_03617281, RAD0 => READ_ADDR_A(0), RAD1 => READ_ADDR_A(1), RAD2 => READ_ADDR_A(2), RAD3 => READ_ADDR_A(3), RAD4 => READ_ADDR_A(4), WAD0 => WRITE_ADDR_A(0), WAD1 => WRITE_ADDR_A(1), WAD2 => WRITE_ADDR_A(2), WAD3 => WRITE_ADDR_A(3), WAD4 => WRITE_ADDR_A(4), WPE0 => N_03617283, WPE1 => N_03617283, WREN => wren_A ); I_03612170 : VHI port map( Z => N_03617282 ); I_03612171 : VHI port map( Z => N_03617283 ); I_03612174 : VHI port map( Z => N_03617273 ); I_03612211 : fifo_controller port map( CLEAR => clear_fifo_A, CLK => CLK, EMPTY => empty_A, FULL => full_A, READ => read_A, READ_ADDR(4 downto 0) => READ_ADDR_A(4 downto 0), RST => RST, WREN => wren_A, WRITE => write_A, WRITE_ADDR(4 downto 0) => WRITE_ADDR_A(4 downto 0) ); I_03612220 : fifo_controller port map( CLEAR => clear_fifo_B, CLK => CLK, EMPTY => empty_B, FULL => full_B, READ => read_B, READ_ADDR(4 downto 0) => READ_ADDR_B(4 downto 0), RST => RST, WREN => wren_B, WRITE => write_B, WRITE_ADDR(4 downto 0) => WRITE_ADDR_B(4 downto 0) ); I_03612229 : DCE32X4 port map( CK => CLK, DI0 => DI_B(4), DI1 => DI_B(5), DI2 => DI_B(6), DI3 => DI_B(7), DO0 => N_03617328, DO1 => N_03617329, DO2 => N_03617330, DO3 => N_03617331, QDO0 => QDO_B(4), QDO1 => QDO_B(5), QDO2 => QDO_B(6), QDO3 => QDO_B(7), RAD0 => READ_ADDR_A(0), RAD1 => READ_ADDR_A(1), RAD2 => READ_ADDR_A(2), RAD3 => READ_ADDR_A(3), RAD4 => READ_ADDR_A(4), WAD0 => WRITE_ADDR_B(0), WAD1 => WRITE_ADDR_B(1), WAD2 => WRITE_ADDR_B(2), WAD3 => WRITE_ADDR_B(3), WAD4 => WRITE_ADDR_B(4), WPE0 => N_03617366, WPE1 => N_03617366, WREN => wren_B ); I_03612230 : DCE32X4 port map( CK => CLK, DI0 => DI_B(8), DI1 => DI_B(9), DI2 => DI_B(10), DI3 => N_03617350, DO0 => N_03617332, DO1 => N_03617333, DO2 => N_03617334, DO3 => N_03617335, QDO0 => QDO_B(8), QDO1 => QDO_B(9), QDO2 => QDO_B(10), QDO3 => N_03617365, RAD0 => READ_ADDR_A(0), RAD1 => READ_ADDR_A(1), RAD2 => READ_ADDR_A(2), RAD3 => READ_ADDR_A(3), RAD4 => READ_ADDR_A(4), WAD0 => WRITE_ADDR_B(0), WAD1 => WRITE_ADDR_B(1), WAD2 => WRITE_ADDR_B(2), WAD3 => WRITE_ADDR_B(3), WAD4 => WRITE_ADDR_B(4), WPE0 => N_03617367, WPE1 => N_03617367, WREN => wren_B ); I_03612231 : DCE32X4 port map( CK => CLK, DI0 => DI_B(0), DI1 => DI_B(1), DI2 => DI_B(2), DI3 => DI_B(3), DO0 => N_03617340, DO1 => N_03617351, DO2 => N_03617352, DO3 => N_03617353, QDO0 => QDO_B(0), QDO1 => QDO_B(1), QDO2 => QDO_B(2), QDO3 => QDO_B(3), RAD0 => READ_ADDR_B(0), RAD1 => READ_ADDR_B(1), RAD2 => READ_ADDR_B(2), RAD3 => READ_ADDR_B(3), RAD4 => READ_ADDR_B(4), WAD0 => WRITE_ADDR_B(0), WAD1 => WRITE_ADDR_B(1), WAD2 => WRITE_ADDR_B(2), WAD3 => WRITE_ADDR_B(3), WAD4 => WRITE_ADDR_B(4), WPE0 => N_03617342, WPE1 => N_03617342, WREN => wren_B ); I_03612232 : VHI port map( Z => N_03617342 ); I_03612233 : VHI port map( Z => N_03617366 ); I_03612234 : VHI port map( Z => N_03617367 ); I_03612238 : VHI port map( Z => N_03617350 ); I_0362531 : VLO port map( Z => N_0363584 ); I_0362532 : CLKCNTLT port map( CLKIN => INPUT_CLK, CLKOUT => CLK, SHUTOFF => N_0363584 ); rstn : IBTPU port map( I => RST, O => GSRNET ); gsr0 : GSR port map( GSR => GSRNET ); I_036307 : histo_circ port map( BASE_ADDRESS(7 downto 0) => N_03615681(7 downto 0), BS_MB2(2 downto 0) => local_BS_MB2(2 downto 0), BS_MB3(2 downto 0) => local_BS_MB3(2 downto 0), BUSY => N_03616492, CLK => CLK, G_MB2(1 downto 0) => G_MB2_INT(1 downto 0), G_MB3(1 downto 0) => G_MB3_INT(1 downto 0), LOAD_BASE_ADDRESS => N_03614231, MEM2_TRISTATE(3 downto 0) => MEM2_TRISTATE(3 downto 0), MEM3_TRISTATE(3 downto 0) => MEM3_TRISTATE(3 downto 0), MEMORY_CLEAR => N_03613943, MEM_ADDR_MB2(18 downto 0) => MEM_ADDR_MB2_INT(18 downto 0), MEM_ADDR_MB3(18 downto 0) => MEM_ADDR_MB3_INT(18 downto 0), MEM_DATAH_MB2_I(8 downto 0) => MEM_DATAH_MB2_I(8 downto 0), MEM_DATAH_MB2_O(8 downto 0) => MEM_DATAH_MB2_O(8 downto 0), MEM_DATAH_MB3_I(8 downto 0) => MEM_DATAH_MB3_I(8 downto 0), MEM_DATAH_MB3_O(8 downto 0) => MEM_DATAH_MB3_O(8 downto 0), MEM_DATAL_MB2_I(8 downto 0) => MEM_DATAL_MB2_I(8 downto 0), MEM_DATAL_MB2_O(8 downto 0) => MEM_DATAL_MB2_O(8 downto 0), MEM_DATAL_MB3_I(8 downto 0) => MEM_DATAL_MB3_I(8 downto 0), MEM_DATAL_MB3_O(8 downto 0) => MEM_DATAL_MB3_O(8 downto 0), READ => N_03612318, RST => RST, START_HISTOGRAMMING => N_03613047, STOP_HISTOGRAMMING => N_03613048, SW_MB2 => SW_MB2_INT, SW_MB3 => SW_MB3_INT, VME_READ_DATA(31 downto 0) => N_03613044(31 downto 0), channel_A(6 downto 0) => QDO_A(10 downto 4), channel_B(6 downto 0) => QDO_B(10 downto 4), chip_A(3 downto 0) => QDO_A(3 downto 0), chip_B(3 downto 0) => QDO_B(3 downto 0), clear_fifo_A => clear_fifo_A, clear_fifo_B => clear_fifo_B, empty_A => empty_A, empty_B => empty_B, full_A => full_A, full_B => full_B, read_A => read_A, read_B => read_B ); I_03643 : module_controller port map( BS_MB0(2 downto 0) => local_BS_MB0(2 downto 0), BS_MB1(2 downto 0) => local_BS_MB1(2 downto 0), BUSY => N_03613713, CLK => CLK, DIFFERENCE_FOUND => N_03613730, G_MB0(1 downto 0) => G_MB0_INT(1 downto 0), G_MB1(1 downto 0) => G_MB1_INT(1 downto 0), LOAD => N_03613717, MEM0_TRISTATE(3 downto 0) => MEM0_TRISTATE(3 downto 0), MEM1_TRISTATE(3 downto 0) => MEM1_TRISTATE(3 downto 0), MEM_ADDR_MB0(18 downto 0) => MEM_ADDR_MB0_INT(18 downto 0), MEM_ADDR_MB1(18 downto 0) => MEM_ADDR_MB1_INT(18 downto 0), MEM_DATAH_MB0_I(8 downto 0) => MEM_DATAH_MB0_I(8 downto 0), MEM_DATAH_MB0_O(8 downto 0) => MEM_DATAH_MB0_O(8 downto 0), MEM_DATAH_MB1_I(8 downto 0) => MEM_DATAH_MB1_I(8 downto 0), MEM_DATAH_MB1_O(8 downto 0) => MEM_DATAH_MB1_O(8 downto 0), MEM_DATAL_MB0_I(8 downto 0) => MEM_DATAL_MB0_I(8 downto 0), MEM_DATAL_MB0_O(8 downto 0) => MEM_DATAL_MB0_O(8 downto 0), MEM_DATAL_MB1_I(8 downto 0) => MEM_DATAL_MB1_I(8 downto 0), MEM_DATAL_MB1_O(8 downto 0) => MEM_DATAL_MB1_O(8 downto 0), OUTFIFO_DATA(17 downto 0) => N_03613714(17 downto 0), READ_FROM_FIFO => read_TV_data, RECEIVE_DATA => receive_TV_data, RESET_FIFO => N_03613715, RESYNC_FIFO_DATA(17 downto 0) => rsfifo_data_int(17 downto 0), RESYNC_FIFO_RST => reset_resync_fifo, RST => RST, RUNNING => N_03614248, SEND_FIFO => N_03613511, SIM_MEM_CNT_RST => N_03613946, SIM_MEM_WRITE => N_03613043, START => N_03614241, SW_MB0 => SW_MB0_INT, SW_MB1 => SW_MB1_INT, TV_MEM_CNT_RST => N_03613046, TV_MEM_WRITE => N_03613737, VME_DATA(17 downto 0) => N_03613053(17 downto 0) ); I_0364526 : IFS1P3DX port map( CD => RST, D => N_0365735, Q => N_0365737, SCLK => CLK, SP => N_0365828 ); I_0364527 : OFS1P3DX port map( CD => RST, D => N_0365741, Q => N_0365739, SCLK => CLK, SP => N_0365829 ); I_0364528 : IFS1P3DX port map( CD => RST, D => N_0365740, Q => N_0365742, SCLK => CLK, SP => N_0365830 ); I_0364529 : OFS1P3DX port map( CD => RST, D => N_0365746, Q => N_0365744, SCLK => CLK, SP => N_0365831 ); I_0364530 : IFS1P3DX port map( CD => RST, D => N_0365745, Q => N_0365747, SCLK => CLK, SP => N_0365832 ); I_0364531 : OFS1P3DX port map( CD => RST, D => N_0365752, Q => N_0365749, SCLK => CLK, SP => N_0365833 ); I_0364532 : IFS1P3DX port map( CD => RST, D => N_0365750, Q => N_0365753, SCLK => CLK, SP => N_0365834 ); I_0364533 : OFS1P3DX port map( CD => RST, D => N_0365757, Q => N_0365755, SCLK => CLK, SP => N_0365835 ); I_0364534 : IFS1P3DX port map( CD => RST, D => N_0365756, Q => N_0365758, SCLK => CLK, SP => N_0365836 ); I_0364535 : OFS1P3DX port map( CD => RST, D => N_0365762, Q => N_0365760, SCLK => CLK, SP => N_0365837 ); I_0364536 : IFS1P3DX port map( CD => RST, D => N_0365761, Q => N_0365763, SCLK => CLK, SP => N_0365838 ); I_0364537 : OFS1P3DX port map( CD => RST, D => N_0365767, Q => N_0365765, SCLK => CLK, SP => N_0365839 ); I_0364538 : IFS1P3DX port map( CD => RST, D => N_0365766, Q => N_0365768, SCLK => CLK, SP => N_0365840 ); I_0364539 : IFS1P3DX port map( CD => RST, D => N_0365643, Q => N_0365645, SCLK => CLK, SP => N_0365796 ); I_0364540 : OFS1P3DX port map( CD => RST, D => N_0365650, Q => N_0365647, SCLK => CLK, SP => N_0365797 ); I_0364541 : IFS1P3DX port map( CD => RST, D => N_0365648, Q => N_0365651, SCLK => CLK, SP => N_0365798 ); I_0364542 : OFS1P3DX port map( CD => RST, D => N_0365655, Q => N_0365653, SCLK => CLK, SP => N_0365799 ); I_0364543 : IFS1P3DX port map( CD => RST, D => N_0365654, Q => N_0365656, SCLK => CLK, SP => N_0365800 ); I_0364544 : OFS1P3DX port map( CD => RST, D => N_0365660, Q => N_0365658, SCLK => CLK, SP => N_0365801 ); I_0364545 : IFS1P3DX port map( CD => RST, D => N_0365659, Q => N_0365661, SCLK => CLK, SP => N_0365802 ); I_0364546 : OFS1P3DX port map( CD => RST, D => N_0365665, Q => N_0365663, SCLK => CLK, SP => N_0365803 ); I_0364547 : IFS1P3DX port map( CD => RST, D => N_0365664, Q => N_0365666, SCLK => CLK, SP => N_0365804 ); I_0364548 : OFS1P3DX port map( CD => RST, D => N_0365672, Q => N_0365668, SCLK => CLK, SP => N_0365805 ); I_0364549 : IFS1P3DX port map( CD => RST, D => N_0365669, Q => N_0365674, SCLK => CLK, SP => N_0365806 ); I_0364550 : OFS1P3DX port map( CD => RST, D => N_0365680, Q => N_0365678, SCLK => CLK, SP => N_0365807 ); I_0364551 : IFS1P3DX port map( CD => RST, D => N_0365679, Q => N_0365681, SCLK => CLK, SP => N_0365808 ); I_0364552 : OFS1P3DX port map( CD => RST, D => N_0365685, Q => N_0365683, SCLK => CLK, SP => N_0365809 ); I_0364553 : IFS1P3DX port map( CD => RST, D => N_0365684, Q => N_0365686, SCLK => CLK, SP => N_0365810 ); I_0364554 : OFS1P3DX port map( CD => RST, D => N_0365690, Q => N_0365688, SCLK => CLK, SP => N_0365811 ); I_0364555 : IFS1P3DX port map( CD => RST, D => N_0365689, Q => N_0365691, SCLK => CLK, SP => N_0365812 ); I_0364556 : OFS1P3DX port map( CD => RST, D => N_0365695, Q => N_0365693, SCLK => CLK, SP => N_0365813 ); I_0364557 : IFS1P3DX port map( CD => RST, D => N_0365694, Q => N_0365696, SCLK => CLK, SP => N_0365814 ); I_0364558 : OFS1P3DX port map( CD => RST, D => N_0365701, Q => N_0365698, SCLK => CLK, SP => N_0365815 ); I_0364559 : IFS1P3DX port map( CD => RST, D => N_0365699, Q => N_0365702, SCLK => CLK, SP => N_0365816 ); I_0364560 : OFS1P3DX port map( CD => RST, D => N_0365706, Q => N_0365704, SCLK => CLK, SP => N_0365817 ); I_0364561 : IFS1P3DX port map( CD => RST, D => N_0365705, Q => N_0365707, SCLK => CLK, SP => N_0365818 ); I_0364562 : OFS1P3DX port map( CD => RST, D => N_0365711, Q => N_0365709, SCLK => CLK, SP => N_0365819 ); I_0364563 : IFS1P3DX port map( CD => RST, D => N_0365710, Q => N_0365712, SCLK => CLK, SP => N_0365820 ); I_0364564 : OFS1P3DX port map( CD => RST, D => N_0365716, Q => N_0365714, SCLK => CLK, SP => N_0365821 ); I_0364565 : IFS1P3DX port map( CD => RST, D => N_0365715, Q => N_0365717, SCLK => CLK, SP => N_0365822 ); I_0364566 : OFS1P3DX port map( CD => RST, D => N_0365723, Q => N_0365719, SCLK => CLK, SP => N_0365823 ); I_0364567 : IFS1P3DX port map( CD => RST, D => N_0365720, Q => N_0365725, SCLK => CLK, SP => N_0365824 ); I_0364568 : OFS1P3DX port map( CD => RST, D => N_0365731, Q => N_0365729, SCLK => CLK, SP => N_0365825 ); I_0364569 : IFS1P3DX port map( CD => RST, D => N_0365730, Q => N_0365732, SCLK => CLK, SP => N_0365826 ); I_0364570 : OFS1P3DX port map( CD => RST, D => N_0365736, Q => N_0365734, SCLK => CLK, SP => N_0365827 ); I_0364571 : VHI port map( Z => N_0365840 ); I_0364576 : OFS1P3DX port map( CD => RST, D => N_0365569, Q => N_0365566, SCLK => CLK, SP => N_0365769 ); I_0364577 : IFS1P3DX port map( CD => RST, D => N_0365567, Q => N_0365571, SCLK => CLK, SP => N_0365770 ); I_0364578 : OFS1P3DX port map( CD => RST, D => N_0365578, Q => N_0365576, SCLK => CLK, SP => N_0365771 ); I_0364579 : IFS1P3DX port map( CD => RST, D => N_0365577, Q => N_0365579, SCLK => CLK, SP => N_0365772 ); I_0364580 : OFS1P3DX port map( CD => RST, D => N_0365583, Q => N_0365581, SCLK => CLK, SP => N_0365773 ); I_0364581 : IFS1P3DX port map( CD => RST, D => N_0365582, Q => N_0365584, SCLK => CLK, SP => N_0365774 ); I_0364582 : OFS1P3DX port map( CD => RST, D => N_0365588, Q => N_0365586, SCLK => CLK, SP => N_0365775 ); I_0364583 : IFS1P3DX port map( CD => RST, D => N_0365587, Q => N_0365589, SCLK => CLK, SP => N_0365776 ); I_0364584 : OFS1P3DX port map( CD => RST, D => N_0365593, Q => N_0365591, SCLK => CLK, SP => N_0365777 ); I_0364585 : IFS1P3DX port map( CD => RST, D => N_0365592, Q => N_0365594, SCLK => CLK, SP => N_0365778 ); I_0364586 : OFS1P3DX port map( CD => RST, D => N_0365599, Q => N_0365596, SCLK => CLK, SP => N_0365779 ); I_0364587 : IFS1P3DX port map( CD => RST, D => N_0365597, Q => N_0365600, SCLK => CLK, SP => N_0365780 ); I_0364588 : OFS1P3DX port map( CD => RST, D => N_0365604, Q => N_0365602, SCLK => CLK, SP => N_0365781 ); I_0364589 : IFS1P3DX port map( CD => RST, D => N_0365603, Q => N_0365605, SCLK => CLK, SP => N_0365782 ); I_0364590 : OFS1P3DX port map( CD => RST, D => N_0365609, Q => N_0365607, SCLK => CLK, SP => N_0365783 ); I_0364591 : IFS1P3DX port map( CD => RST, D => N_0365608, Q => N_0365610, SCLK => CLK, SP => N_0365784 ); I_0364592 : OFS1P3DX port map( CD => RST, D => N_0365614, Q => N_0365612, SCLK => CLK, SP => N_0365785 ); I_0364593 : IFS1P3DX port map( CD => RST, D => N_0365613, Q => N_0365615, SCLK => CLK, SP => N_0365786 ); I_0364594 : OFS1P3DX port map( CD => RST, D => N_0365621, Q => N_0365617, SCLK => CLK, SP => N_0365787 ); I_0364595 : IFS1P3DX port map( CD => RST, D => N_0365618, Q => N_0365623, SCLK => CLK, SP => N_0365788 ); I_0364596 : OFS1P3DX port map( CD => RST, D => N_0365629, Q => N_0365627, SCLK => CLK, SP => N_0365789 ); I_0364597 : IFS1P3DX port map( CD => RST, D => N_0365628, Q => N_0365630, SCLK => CLK, SP => N_0365790 ); I_0364598 : OFS1P3DX port map( CD => RST, D => N_0365634, Q => N_0365632, SCLK => CLK, SP => N_0365791 ); I_0364599 : IFS1P3DX port map( CD => RST, D => N_0365633, Q => N_0365635, SCLK => CLK, SP => N_0365792 ); I_0364600 : OFS1P3DX port map( CD => RST, D => N_0365639, Q => N_0365637, SCLK => CLK, SP => N_0365793 ); I_0364601 : IFS1P3DX port map( CD => RST, D => N_0365638, Q => N_0365640, SCLK => CLK, SP => N_0365794 ); I_0364602 : OFS1P3DX port map( CD => RST, D => N_0365644, Q => N_0365642, SCLK => CLK, SP => N_0365795 ); I_0364603 : BMZ12FPU port map( B => MEM_DATAL_MB1(3), I => N_0365739, O => N_0365740, T => N_0365721 ); I_0364604 : VHI port map( Z => N_0365829 ); I_0364605 : VHI port map( Z => N_0365830 ); I_0364609 : BMZ12FPU port map( B => MEM_DATAL_MB1(4), I => N_0365744, O => N_0365745, T => N_0365721 ); I_0364610 : VHI port map( Z => N_0365831 ); I_0364611 : VHI port map( Z => N_0365832 ); I_0364615 : BMZ12FPU port map( B => MEM_DATAL_MB1(5), I => N_0365749, O => N_0365750, T => N_0365751 ); I_0364616 : VHI port map( Z => N_0365833 ); I_0364617 : VHI port map( Z => N_0365834 ); I_0364621 : BMZ12FPU port map( B => MEM_DATAL_MB1(6), I => N_0365755, O => N_0365756, T => N_0365751 ); I_0364622 : VHI port map( Z => N_0365835 ); I_0364623 : VHI port map( Z => N_0365836 ); I_0364627 : BMZ12FPU port map( B => MEM_DATAL_MB1(7), I => N_0365760, O => N_0365761, T => N_0365751 ); I_0364628 : VHI port map( Z => N_0365837 ); I_0364629 : VHI port map( Z => N_0365838 ); I_0364633 : BMZ12FPU port map( B => MEM_DATAL_MB1(8), I => N_0365765, O => N_0365766, T => N_0365751 ); I_0364634 : VHI port map( Z => N_0365839 ); I_0364636 : BMZ12FPU port map( B => MEM_DATAH_MB1(7), I => N_0365709, O => N_0365710, T => N_0367197 ); I_0364637 : VHI port map( Z => N_0365819 ); I_0364638 : VHI port map( Z => N_0365820 ); I_0364642 : BMZ12FPU port map( B => MEM_DATAH_MB1(8), I => N_0365714, O => N_0365715, T => N_0367197 ); I_0364643 : VHI port map( Z => N_0365821 ); I_0364644 : VHI port map( Z => N_0365822 ); I_0364649 : BMZ12FPU port map( B => MEM_DATAL_MB1(0), I => N_0365719, O => N_0365720, T => N_0365721 ); I_0364650 : VHI port map( Z => N_0365823 ); I_0364651 : VHI port map( Z => N_0365824 ); I_0364655 : BMZ12FPU port map( B => MEM_DATAL_MB1(1), I => N_0365729, O => N_0365730, T => N_0365721 ); I_0364656 : VHI port map( Z => N_0365825 ); I_0364657 : VHI port map( Z => N_0365826 ); I_0364661 : BMZ12FPU port map( B => MEM_DATAL_MB1(2), I => N_0365734, O => N_0365735, T => N_0365721 ); I_0364662 : VHI port map( Z => N_0365827 ); I_0364663 : VHI port map( Z => N_0365828 ); I_0364670 : BMZ12FPU port map( B => MEM_DATAH_MB1(2), I => N_0365683, O => N_0365684, T => N_0367194 ); I_0364671 : VHI port map( Z => N_0365809 ); I_0364672 : VHI port map( Z => N_0365810 ); I_0364676 : BMZ12FPU port map( B => MEM_DATAH_MB1(3), I => N_0365688, O => N_0365689, T => N_0367194 ); I_0364677 : VHI port map( Z => N_0365811 ); I_0364678 : VHI port map( Z => N_0365812 ); I_0364682 : BMZ12FPU port map( B => MEM_DATAH_MB1(4), I => N_0365693, O => N_0365694, T => N_0367194 ); I_0364683 : VHI port map( Z => N_0365813 ); I_0364684 : VHI port map( Z => N_0365814 ); I_0364688 : BMZ12FPU port map( B => MEM_DATAH_MB1(5), I => N_0365698, O => N_0365699, T => N_0367197 ); I_0364689 : VHI port map( Z => N_0365815 ); I_0364690 : VHI port map( Z => N_0365816 ); I_0364694 : BMZ12FPU port map( B => MEM_DATAH_MB1(6), I => N_0365704, O => N_0365705, T => N_0367197 ); I_0364695 : VHI port map( Z => N_0365817 ); I_0364696 : VHI port map( Z => N_0365818 ); I_0364699 : VHI port map( Z => N_0365798 ); I_0364703 : BMZ12FPU port map( B => MEM_DATAL_MB0(6), I => N_0365653, O => N_0365654, T => N_0367406 ); I_0364704 : VHI port map( Z => N_0365799 ); I_0364705 : VHI port map( Z => N_0365800 ); I_0364709 : BMZ12FPU port map( B => MEM_DATAL_MB0(7), I => N_0365658, O => N_0365659, T => N_0367406 ); I_0364710 : VHI port map( Z => N_0365801 ); I_0364711 : VHI port map( Z => N_0365802 ); I_0364715 : BMZ12FPU port map( B => MEM_DATAL_MB0(8), I => N_0365663, O => N_0365664, T => N_0367406 ); I_0364716 : VHI port map( Z => N_0365803 ); I_0364717 : VHI port map( Z => N_0365804 ); I_0364722 : BMZ12FPU port map( B => MEM_DATAH_MB1(0), I => N_0365668, O => N_0365669, T => N_0367194 ); I_0364723 : VHI port map( Z => N_0365805 ); I_0364724 : VHI port map( Z => N_0365806 ); I_0364728 : BMZ12FPU port map( B => MEM_DATAH_MB1(1), I => N_0365678, O => N_0365679, T => N_0367194 ); I_0364729 : VHI port map( Z => N_0365807 ); I_0364730 : VHI port map( Z => N_0365808 ); I_0364731 : BMZ12FPU port map( B => MEM_DATAL_MB0(0), I => N_0365617, O => N_0365618, T => N_0367399 ); I_0364732 : VHI port map( Z => N_0365787 ); I_0364733 : VHI port map( Z => N_0365788 ); I_0364737 : BMZ12FPU port map( B => MEM_DATAL_MB0(1), I => N_0365627, O => N_0365628, T => N_0367399 ); I_0364738 : VHI port map( Z => N_0365789 ); I_0364739 : VHI port map( Z => N_0365790 ); I_0364743 : BMZ12FPU port map( B => MEM_DATAL_MB0(2), I => N_0365632, O => N_0365633, T => N_0367399 ); I_0364744 : VHI port map( Z => N_0365791 ); I_0364745 : VHI port map( Z => N_0365792 ); I_0364749 : BMZ12FPU port map( B => MEM_DATAL_MB0(3), I => N_0365637, O => N_0365638, T => N_0367399 ); I_0364750 : VHI port map( Z => N_0365793 ); I_0364751 : VHI port map( Z => N_0365794 ); I_0364755 : BMZ12FPU port map( B => MEM_DATAL_MB0(4), I => N_0365642, O => N_0365643, T => N_0367399 ); I_0364756 : VHI port map( Z => N_0365795 ); I_0364757 : VHI port map( Z => N_0365796 ); I_0364761 : BMZ12FPU port map( B => MEM_DATAL_MB0(5), I => N_0365647, O => N_0365648, T => N_0367406 ); I_0364762 : VHI port map( Z => N_0365797 ); I_0364764 : BMZ12FPU port map( B => MEM_DATAH_MB0(4), I => N_0365591, O => N_0365592, T => N_0367402 ); I_0364765 : VHI port map( Z => N_0365777 ); I_0364766 : VHI port map( Z => N_0365778 ); I_0364770 : BMZ12FPU port map( B => MEM_DATAH_MB0(5), I => N_0365596, O => N_0365597, T => N_0367404 ); I_0364771 : VHI port map( Z => N_0365779 ); I_0364772 : VHI port map( Z => N_0365780 ); I_0364776 : BMZ12FPU port map( B => MEM_DATAH_MB0(6), I => N_0365602, O => N_0365603, T => N_0367404 ); I_0364777 : VHI port map( Z => N_0365781 ); I_0364778 : VHI port map( Z => N_0365782 ); I_0364782 : BMZ12FPU port map( B => MEM_DATAH_MB0(7), I => N_0365607, O => N_0365608, T => N_0367404 ); I_0364783 : VHI port map( Z => N_0365783 ); I_0364784 : VHI port map( Z => N_0365784 ); I_0364788 : BMZ12FPU port map( B => MEM_DATAH_MB0(8), I => N_0365612, O => N_0365613, T => N_0367404 ); I_0364789 : VHI port map( Z => N_0365785 ); I_0364790 : VHI port map( Z => N_0365786 ); I_0364795 : VHI port map( Z => N_0365556 ); I_0364796 : VHI port map( Z => N_0365557 ); I_0364797 : VHI port map( Z => N_0365558 ); I_0364798 : VHI port map( Z => N_0365559 ); I_0364799 : VHI port map( Z => N_0365560 ); I_0364800 : VHI port map( Z => N_0365561 ); I_0364801 : VHI port map( Z => N_0365562 ); I_0364802 : VHI port map( Z => N_0365563 ); I_0364803 : VHI port map( Z => N_0365564 ); I_0364804 : BMZ12FPU port map( B => MEM_DATAH_MB0(0), I => N_0365566, O => N_0365567, T => N_0367402 ); I_0364805 : VHI port map( Z => N_0365769 ); I_0364806 : VHI port map( Z => N_0365770 ); I_0364810 : BMZ12FPU port map( B => MEM_DATAH_MB0(1), I => N_0365576, O => N_0365577, T => N_0367402 ); I_0364811 : VHI port map( Z => N_0365771 ); I_0364812 : VHI port map( Z => N_0365772 ); I_0364816 : BMZ12FPU port map( B => MEM_DATAH_MB0(2), I => N_0365581, O => N_0365582, T => N_0367402 ); I_0364817 : VHI port map( Z => N_0365773 ); I_0364818 : VHI port map( Z => N_0365774 ); I_0364822 : BMZ12FPU port map( B => MEM_DATAH_MB0(3), I => N_0365586, O => N_0365587, T => N_0367402 ); I_0364823 : VHI port map( Z => N_0365775 ); I_0364824 : VHI port map( Z => N_0365776 ); I_0364831 : OFS1P3DX port map( CD => RST, D => N_0365536, Q => local_OUTFIFO_DATA(12), SCLK => CLK, SP => N_0365559 ); I_0364833 : OFS1P3DX port map( CD => RST, D => N_0365538, Q => local_OUTFIFO_DATA(13), SCLK => CLK, SP => N_0365560 ); I_0364834 : OFS1P3DX port map( CD => RST, D => N_0365540, Q => local_OUTFIFO_DATA(14), SCLK => CLK, SP => N_0365561 ); I_0364835 : OFS1P3DX port map( CD => RST, D => N_0365542, Q => local_OUTFIFO_DATA(15), SCLK => CLK, SP => N_0365562 ); I_0364836 : OFS1P3DX port map( CD => RST, D => N_0365544, Q => local_OUTFIFO_DATA(16), SCLK => CLK, SP => N_0365563 ); I_0364837 : OFS1P3DX port map( CD => RST, D => N_0365546, Q => local_OUTFIFO_DATA(17), SCLK => CLK, SP => N_0365564 ); I_0364850 : VHI port map( Z => N_0365513 ); I_0364851 : VHI port map( Z => N_0365548 ); I_0364852 : VHI port map( Z => N_0365549 ); I_0364853 : VHI port map( Z => N_0365550 ); I_0364854 : VHI port map( Z => N_0365551 ); I_0364855 : VHI port map( Z => N_0365552 ); I_0364856 : VHI port map( Z => N_0365553 ); I_0364857 : VHI port map( Z => N_0365554 ); I_0364858 : VHI port map( Z => N_0365555 ); I_0364859 : OFS1P3DX port map( CD => RST, D => N_0365510, Q => local_OUTFIFO_DATA(0), SCLK => CLK, SP => N_0365513 ); I_0364861 : OFS1P3DX port map( CD => RST, D => N_0365519, Q => local_OUTFIFO_DATA(1), SCLK => CLK, SP => N_0365548 ); I_0364862 : OFS1P3DX port map( CD => RST, D => N_0365520, Q => local_OUTFIFO_DATA(2), SCLK => CLK, SP => N_0365549 ); I_0364863 : OFS1P3DX port map( CD => RST, D => N_0365521, Q => local_OUTFIFO_DATA(3), SCLK => CLK, SP => N_0365550 ); I_0364864 : OFS1P3DX port map( CD => RST, D => N_0365522, Q => local_OUTFIFO_DATA(4), SCLK => CLK, SP => N_0365551 ); I_0364865 : OFS1P3DX port map( CD => RST, D => N_0365523, Q => local_OUTFIFO_DATA(5), SCLK => CLK, SP => N_0365552 ); I_0364877 : OFS1P3DX port map( CD => RST, D => N_0365524, Q => local_OUTFIFO_DATA(6), SCLK => CLK, SP => N_0365553 ); I_0364879 : OFS1P3DX port map( CD => RST, D => N_0365531, Q => local_OUTFIFO_DATA(7), SCLK => CLK, SP => N_0365554 ); I_0364880 : OFS1P3DX port map( CD => RST, D => N_0365532, Q => local_OUTFIFO_DATA(8), SCLK => CLK, SP => N_0365555 ); I_0364881 : OFS1P3DX port map( CD => RST, D => N_0365533, Q => local_OUTFIFO_DATA(9), SCLK => CLK, SP => N_0365556 ); I_0364882 : OFS1P3DX port map( CD => RST, D => N_0365534, Q => local_OUTFIFO_DATA(10), SCLK => CLK, SP => N_0365557 ); I_0364883 : OFS1P3DX port map( CD => RST, D => N_0365535, Q => local_OUTFIFO_DATA(11), SCLK => CLK, SP => N_0365558 ); I_036512 : test_connector port map( CLK => CLK, LAST_COMMAND(4 downto 0) => N_03614249(4 downto 0), LED(8 downto 0) => local_LED(8 downto 0), RST => RST, RUNNING => N_036626, TC(19 downto 0) => local_TC(19 downto 0), VALID_VME_ACCESS => N_03614455, t0 => N_03612520, t1 => N_03612521, t2 => N_03612522, t3 => N_03612523, t4 => N_03612524, t5 => N_03612525, t6 => N_03612526, t7 => N_03612527, t8 => N_03612528, t9 => N_03612529 ); I_0365509 : OFS1P3DX port map( CD => RST, D => N_0367666, Q => local_MEM_ADDR_MB0(0), SCLK => CLK, SP => N_0367669 ); I_0365511 : OFS1P3DX port map( CD => RST, D => N_0367670, Q => local_MEM_ADDR_MB0(1), SCLK => CLK, SP => N_0367672 ); I_0365512 : OFS1P3DX port map( CD => RST, D => N_0367673, Q => local_MEM_ADDR_MB0(2), SCLK => CLK, SP => N_0367675 ); I_0365513 : OFS1P3DX port map( CD => RST, D => N_0367676, Q => local_MEM_ADDR_MB0(3), SCLK => CLK, SP => N_0367678 ); I_0365514 : OFS1P3DX port map( CD => RST, D => N_0367679, Q => local_MEM_ADDR_MB0(4), SCLK => CLK, SP => N_0367681 ); I_0365515 : OFS1P3DX port map( CD => RST, D => N_0367682, Q => local_MEM_ADDR_MB0(5), SCLK => CLK, SP => N_0367684 ); I_0365527 : OFS1P3DX port map( CD => RST, D => N_0367686, Q => local_MEM_ADDR_MB0(6), SCLK => CLK, SP => N_0367688 ); I_0365529 : OFS1P3DX port map( CD => RST, D => N_0367689, Q => local_MEM_ADDR_MB0(7), SCLK => CLK, SP => N_0367691 ); I_0365530 : OFS1P3DX port map( CD => RST, D => N_0367692, Q => local_MEM_ADDR_MB0(8), SCLK => CLK, SP => N_0367694 ); I_0365531 : OFS1P3DX port map( CD => RST, D => N_0367695, Q => local_MEM_ADDR_MB0(9), SCLK => CLK, SP => N_0367697 ); I_0365532 : OFS1P3DX port map( CD => RST, D => N_0367698, Q => local_MEM_ADDR_MB0(10), SCLK => CLK, SP => N_0367700 ); I_0365533 : OFS1P3DX port map( CD => RST, D => N_0367701, Q => local_MEM_ADDR_MB0(11), SCLK => CLK, SP => N_0367703 ); I_0365545 : OFS1P3DX port map( CD => RST, D => N_0367704, Q => local_MEM_ADDR_MB0(12), SCLK => CLK, SP => N_0367706 ); I_0365547 : OFS1P3DX port map( CD => RST, D => N_0367707, Q => local_MEM_ADDR_MB0(13), SCLK => CLK, SP => N_0367709 ); I_0365548 : OFS1P3DX port map( CD => RST, D => N_0367710, Q => local_MEM_ADDR_MB0(14), SCLK => CLK, SP => N_0367712 ); I_0365549 : OFS1P3DX port map( CD => RST, D => N_0367713, Q => local_MEM_ADDR_MB0(15), SCLK => CLK, SP => N_0367715 ); I_0365550 : OFS1P3DX port map( CD => RST, D => N_0367716, Q => local_MEM_ADDR_MB0(16), SCLK => CLK, SP => N_0367718 ); I_0365551 : OFS1P3DX port map( CD => RST, D => N_0367719, Q => local_MEM_ADDR_MB0(17), SCLK => CLK, SP => N_0367721 ); I_0365564 : VHI port map( Z => N_0367669 ); I_0365565 : VHI port map( Z => N_0367672 ); I_0365566 : VHI port map( Z => N_0367675 ); I_0365567 : VHI port map( Z => N_0367678 ); I_0365568 : VHI port map( Z => N_0367681 ); I_0365569 : VHI port map( Z => N_0367684 ); I_0365570 : VHI port map( Z => N_0367688 ); I_0365571 : VHI port map( Z => N_0367691 ); I_0365572 : VHI port map( Z => N_0367694 ); I_0365573 : VHI port map( Z => N_0367697 ); I_0365574 : VHI port map( Z => N_0367700 ); I_0365575 : VHI port map( Z => N_0367703 ); I_0365576 : VHI port map( Z => N_0367706 ); I_0365577 : VHI port map( Z => N_0367709 ); I_0365578 : VHI port map( Z => N_0367712 ); I_0365579 : VHI port map( Z => N_0367715 ); I_0365580 : VHI port map( Z => N_0367718 ); I_0365581 : VHI port map( Z => N_0367721 ); I_0365584 : OFS1P3DX port map( CD => RST, D => N_0367722, Q => local_MEM_ADDR_MB1(0), SCLK => CLK, SP => N_0367724 ); I_0365586 : OFS1P3DX port map( CD => RST, D => N_0367778, Q => local_SE3_MB1(0), SCLK => CLK, SP => N_0367777 ); I_0365587 : VHI port map( Z => N_0367775 ); I_0365589 : INV port map( A => N_0367783, Z => N_0367779 ); I_0365591 : VHI port map( Z => N_0367777 ); I_0365592 : VHI port map( Z => N_0367751 ); I_0365593 : VHI port map( Z => N_0367754 ); I_0365594 : VHI port map( Z => N_0367757 ); I_0365595 : VHI port map( Z => N_0367760 ); I_0365596 : VHI port map( Z => N_0367763 ); I_0365597 : VHI port map( Z => N_0367766 ); I_0365598 : VHI port map( Z => N_0367769 ); I_0365599 : VHI port map( Z => N_0367772 ); I_0365600 : OFS1P3DX port map( CD => RST, D => N_0367779, Q => local_SE3_MB1(1), SCLK => CLK, SP => N_0367785 ); I_0365603 : VHI port map( Z => N_0367785 ); I_0365608 : OFS1P3DX port map( CD => RST, D => N_0367758, Q => local_MEM_ADDR_MB1(12), SCLK => CLK, SP => N_0367760 ); I_0365610 : OFS1P3DX port map( CD => RST, D => N_0367761, Q => local_MEM_ADDR_MB1(13), SCLK => CLK, SP => N_0367763 ); I_0365611 : OFS1P3DX port map( CD => RST, D => N_0367764, Q => local_MEM_ADDR_MB1(14), SCLK => CLK, SP => N_0367766 ); I_0365612 : OFS1P3DX port map( CD => RST, D => N_0367767, Q => local_MEM_ADDR_MB1(15), SCLK => CLK, SP => N_0367769 ); I_0365613 : OFS1P3DX port map( CD => RST, D => N_0367770, Q => local_MEM_ADDR_MB1(16), SCLK => CLK, SP => N_0367772 ); I_0365614 : OFS1P3DX port map( CD => RST, D => N_0367773, Q => local_MEM_ADDR_MB1(17), SCLK => CLK, SP => N_0367775 ); I_0365625 : VHI port map( Z => N_0367724 ); I_0365626 : VHI port map( Z => N_0367727 ); I_0365627 : VHI port map( Z => N_0367730 ); I_0365628 : VHI port map( Z => N_0367733 ); I_0365629 : VHI port map( Z => N_0367736 ); I_0365630 : VHI port map( Z => N_0367739 ); I_0365631 : VHI port map( Z => N_0367742 ); I_0365632 : VHI port map( Z => N_0367745 ); I_0365633 : VHI port map( Z => N_0367748 ); I_0365634 : OFS1P3DX port map( CD => RST, D => N_0367725, Q => local_MEM_ADDR_MB1(1), SCLK => CLK, SP => N_0367727 ); I_0365635 : OFS1P3DX port map( CD => RST, D => N_0367728, Q => local_MEM_ADDR_MB1(2), SCLK => CLK, SP => N_0367730 ); I_0365636 : OFS1P3DX port map( CD => RST, D => N_0367731, Q => local_MEM_ADDR_MB1(3), SCLK => CLK, SP => N_0367733 ); I_0365637 : OFS1P3DX port map( CD => RST, D => N_0367734, Q => local_MEM_ADDR_MB1(4), SCLK => CLK, SP => N_0367736 ); I_0365638 : OFS1P3DX port map( CD => RST, D => N_0367737, Q => local_MEM_ADDR_MB1(5), SCLK => CLK, SP => N_0367739 ); I_0365650 : OFS1P3DX port map( CD => RST, D => N_0367740, Q => local_MEM_ADDR_MB1(6), SCLK => CLK, SP => N_0367742 ); I_0365652 : OFS1P3DX port map( CD => RST, D => N_0367743, Q => local_MEM_ADDR_MB1(7), SCLK => CLK, SP => N_0367745 ); I_0365653 : OFS1P3DX port map( CD => RST, D => N_0367746, Q => local_MEM_ADDR_MB1(8), SCLK => CLK, SP => N_0367748 ); I_0365654 : OFS1P3DX port map( CD => RST, D => N_0367749, Q => local_MEM_ADDR_MB1(9), SCLK => CLK, SP => N_0367751 ); I_0365655 : OFS1P3DX port map( CD => RST, D => N_0367752, Q => local_MEM_ADDR_MB1(10), SCLK => CLK, SP => N_0367754 ); I_0365656 : OFS1P3DX port map( CD => RST, D => N_0367755, Q => local_MEM_ADDR_MB1(11), SCLK => CLK, SP => N_0367757 ); I_0365665 : OFS1P3DX port map( CD => RST, D => N_0367788, Q => local_SE3_MB0(0), SCLK => CLK, SP => N_0367789 ); I_0365666 : VHI port map( Z => N_0367789 ); I_0365668 : INV port map( A => N_0367794, Z => N_0367790 ); I_0365669 : OFS1P3DX port map( CD => RST, D => N_0367790, Q => local_SE3_MB0(1), SCLK => CLK, SP => N_0367792 ); I_0365672 : VHI port map( Z => N_0367792 ); I_03658 : clk_loader port map( CLK => CLK, CLK_LOAD => N_03614218, M(8 downto 0) => N_03635(8 downto 0), N(1 downto 0) => N_03625(1 downto 0), RST => RST, T(2 downto 0) => N_03614221(2 downto 0), clk_data => local_CLK_DATA, clk_ld => local_CLK_LD, clk_ld_clk => local_CLK_LD_CLK, clk_test => TEST ); I_0365876 : OFS1P3DX port map( CD => RST, D => SW_MB1_INT, Q => local_SW_MB1, SCLK => CLK, SP => N_0368001 ); I_0365877 : OFS1P3DX port map( CD => RST, D => SW_MB0_INT, Q => local_SW_MB0, SCLK => CLK, SP => N_0368003 ); I_0365879 : VHI port map( Z => N_0368001 ); I_0365880 : VHI port map( Z => N_0368003 ); I_0366082 : OFS1P3DX port map( CD => RST, D => N_0368476, Q => local_G_MB1(0), SCLK => CLK, SP => N_0368266 ); I_0366083 : OFS1P3DX port map( CD => RST, D => N_0368477, Q => local_G_MB1(1), SCLK => CLK, SP => N_0368267 ); I_0366084 : VHI port map( Z => N_0368266 ); I_0366085 : VHI port map( Z => N_0368267 ); I_0366086 : OFS1P3DX port map( CD => RST, D => N_0368478, Q => local_G_MB0(0), SCLK => CLK, SP => N_0368271 ); I_0366087 : OFS1P3DX port map( CD => RST, D => N_0368479, Q => local_G_MB0(1), SCLK => CLK, SP => N_0368272 ); I_0366088 : VHI port map( Z => N_0368271 ); I_0366089 : VHI port map( Z => N_0368272 ); I_0366574 : OFS1P3DX port map( CD => RST, D => outfifo_renB_int, Q => local_OUTFIFO_RENB, SCLK => CLK, SP => N_0369101 ); I_0366575 : VHI port map( Z => N_0369101 ); I_0366578 : OFS1P3DX port map( CD => RST, D => outfifo_wenB_int, Q => local_OUTFIFO_WENB, SCLK => CLK, SP => N_0369517 ); I_0366580 : VHI port map( Z => N_0369106 ); I_0366581 : IFS1P3DX port map( CD => RST, D => OUTFIFO_EFB, Q => N_0369093, SCLK => CLK, SP => N_0369106 ); I_0366582 : VHI port map( Z => N_0369100 ); I_0366583 : OFS1P3DX port map( CD => RST, D => outfifo_rtB_int, Q => local_OUTFIFO_RTB, SCLK => CLK, SP => N_0369096 ); I_0366584 : OFS1P3DX port map( CD => RST, D => outfifo_mrsB_int, Q => local_OUTFIFO_MRSB, SCLK => CLK, SP => N_0369097 ); I_0366585 : VHI port map( Z => N_0369096 ); I_0366586 : VHI port map( Z => N_0369097 ); I_0366587 : OFS1P3DX port map( CD => RST, D => outfifo_oenB_int, Q => local_OUTFIFO_OENB, SCLK => CLK, SP => N_0369100 ); I_0366792 : VHI port map( Z => N_0369312 ); I_0366793 : IFS1P3DX port map( CD => RST, D => OUTFIFO_FFB, Q => N_0369722, SCLK => CLK, SP => N_0369312 ); I_0366995 : VHI port map( Z => N_0369517 ); I_0367197 : INV port map( A => N_0369093, Z => outfifo_efB_int ); I_0367198 : INV port map( A => N_0369722, Z => outfifo_ffB_int ); I_0367463 : OFS1P3DX port map( CD => RST, D => N_0369926, Q => local_MEM_ADDR_MB2(0), SCLK => CLK, SP => N_0369929 ); I_0367465 : OFS1P3DX port map( CD => RST, D => N_0369930, Q => local_MEM_ADDR_MB2(1), SCLK => CLK, SP => N_0369932 ); I_0367466 : OFS1P3DX port map( CD => RST, D => N_0369933, Q => local_MEM_ADDR_MB2(2), SCLK => CLK, SP => N_0369935 ); I_0367467 : OFS1P3DX port map( CD => RST, D => N_0369936, Q => local_MEM_ADDR_MB2(3), SCLK => CLK, SP => N_0369938 ); I_0367468 : OFS1P3DX port map( CD => RST, D => N_0369939, Q => local_MEM_ADDR_MB2(4), SCLK => CLK, SP => N_0369941 ); I_0367469 : OFS1P3DX port map( CD => RST, D => N_0369942, Q => local_MEM_ADDR_MB2(5), SCLK => CLK, SP => N_0369944 ); I_0367481 : OFS1P3DX port map( CD => RST, D => N_0369946, Q => local_MEM_ADDR_MB2(6), SCLK => CLK, SP => N_0369948 ); I_0367483 : OFS1P3DX port map( CD => RST, D => N_0369949, Q => local_MEM_ADDR_MB2(7), SCLK => CLK, SP => N_0369951 ); I_0367484 : OFS1P3DX port map( CD => RST, D => N_0369952, Q => local_MEM_ADDR_MB2(8), SCLK => CLK, SP => N_0369954 ); I_0367485 : OFS1P3DX port map( CD => RST, D => N_0369955, Q => local_MEM_ADDR_MB2(9), SCLK => CLK, SP => N_0369957 ); I_0367486 : OFS1P3DX port map( CD => RST, D => N_0369958, Q => local_MEM_ADDR_MB2(10), SCLK => CLK, SP => N_0369960 ); I_0367487 : OFS1P3DX port map( CD => RST, D => N_0369961, Q => local_MEM_ADDR_MB2(11), SCLK => CLK, SP => N_0369963 ); I_0367499 : OFS1P3DX port map( CD => RST, D => N_0369964, Q => local_MEM_ADDR_MB2(12), SCLK => CLK, SP => N_0369966 ); I_0367501 : OFS1P3DX port map( CD => RST, D => N_0369967, Q => local_MEM_ADDR_MB2(13), SCLK => CLK, SP => N_0369969 ); I_0367502 : OFS1P3DX port map( CD => RST, D => N_0369970, Q => local_MEM_ADDR_MB2(14), SCLK => CLK, SP => N_0369972 ); I_0367503 : OFS1P3DX port map( CD => RST, D => N_0369973, Q => local_MEM_ADDR_MB2(15), SCLK => CLK, SP => N_0369975 ); I_0367504 : OFS1P3DX port map( CD => RST, D => N_0369976, Q => local_MEM_ADDR_MB2(16), SCLK => CLK, SP => N_0369978 ); I_0367505 : OFS1P3DX port map( CD => RST, D => N_0369979, Q => local_MEM_ADDR_MB2(17), SCLK => CLK, SP => N_0369981 ); I_0367518 : VHI port map( Z => N_0369929 ); I_0367519 : VHI port map( Z => N_0369932 ); I_0367520 : VHI port map( Z => N_0369935 ); I_0367521 : VHI port map( Z => N_0369938 ); I_0367522 : VHI port map( Z => N_0369941 ); I_0367523 : VHI port map( Z => N_0369944 ); I_0367524 : VHI port map( Z => N_0369948 ); I_0367525 : VHI port map( Z => N_0369951 ); I_0367526 : VHI port map( Z => N_0369954 ); I_0367527 : VHI port map( Z => N_0369957 ); I_0367528 : VHI port map( Z => N_0369960 ); I_0367529 : VHI port map( Z => N_0369963 ); I_0367530 : VHI port map( Z => N_0369966 ); I_0367531 : VHI port map( Z => N_0369969 ); I_0367532 : VHI port map( Z => N_0369972 ); I_0367533 : VHI port map( Z => N_0369975 ); I_0367534 : VHI port map( Z => N_0369978 ); I_0367535 : VHI port map( Z => N_0369981 ); I_0367536 : OFS1P3DX port map( CD => RST, D => N_0369982, Q => local_SE3_MB2(0), SCLK => CLK, SP => N_0369983 ); I_0367537 : VHI port map( Z => N_0369983 ); I_0367539 : INV port map( A => N_0369987, Z => N_0369984 ); I_0367540 : OFS1P3DX port map( CD => RST, D => N_0369984, Q => local_SE3_MB2(1), SCLK => CLK, SP => N_0369986 ); I_0367543 : VHI port map( Z => N_0369986 ); I_0367545 : INV port map( A => N_03610051, Z => N_03610048 ); I_0367546 : OFS1P3DX port map( CD => RST, D => N_03610048, Q => local_SE3_MB3(1), SCLK => CLK, SP => N_03610050 ); I_0367549 : VHI port map( Z => N_03610050 ); I_0367562 : VHI port map( Z => N_0369993 ); I_0367563 : VHI port map( Z => N_0369996 ); I_0367564 : VHI port map( Z => N_0369999 ); I_0367565 : VHI port map( Z => N_03610002 ); I_0367566 : VHI port map( Z => N_03610005 ); I_0367567 : VHI port map( Z => N_03610008 ); I_0367568 : VHI port map( Z => N_03610012 ); I_0367569 : VHI port map( Z => N_03610015 ); I_0367570 : VHI port map( Z => N_03610018 ); I_0367571 : VHI port map( Z => N_03610021 ); I_0367572 : VHI port map( Z => N_03610024 ); I_0367573 : VHI port map( Z => N_03610027 ); I_0367574 : VHI port map( Z => N_03610030 ); I_0367575 : VHI port map( Z => N_03610033 ); I_0367576 : VHI port map( Z => N_03610036 ); I_0367577 : VHI port map( Z => N_03610039 ); I_0367578 : VHI port map( Z => N_03610042 ); I_0367579 : VHI port map( Z => N_03610045 ); I_0367580 : OFS1P3DX port map( CD => RST, D => N_03610046, Q => local_SE3_MB3(0), SCLK => CLK, SP => N_03610047 ); I_0367581 : VHI port map( Z => N_03610047 ); I_0367589 : OFS1P3DX port map( CD => RST, D => N_03610010, Q => local_MEM_ADDR_MB3(6), SCLK => CLK, SP => N_03610012 ); I_0367591 : OFS1P3DX port map( CD => RST, D => N_03610013, Q => local_MEM_ADDR_MB3(7), SCLK => CLK, SP => N_03610015 ); I_0367592 : OFS1P3DX port map( CD => RST, D => N_03610016, Q => local_MEM_ADDR_MB3(8), SCLK => CLK, SP => N_03610018 ); I_0367593 : OFS1P3DX port map( CD => RST, D => N_03610019, Q => local_MEM_ADDR_MB3(9), SCLK => CLK, SP => N_03610021 ); I_0367594 : OFS1P3DX port map( CD => RST, D => N_03610022, Q => local_MEM_ADDR_MB3(10), SCLK => CLK, SP => N_03610024 ); I_0367595 : OFS1P3DX port map( CD => RST, D => N_03610025, Q => local_MEM_ADDR_MB3(11), SCLK => CLK, SP => N_03610027 ); I_0367607 : OFS1P3DX port map( CD => RST, D => N_03610028, Q => local_MEM_ADDR_MB3(12), SCLK => CLK, SP => N_03610030 ); I_0367609 : OFS1P3DX port map( CD => RST, D => N_03610031, Q => local_MEM_ADDR_MB3(13), SCLK => CLK, SP => N_03610033 ); I_0367610 : OFS1P3DX port map( CD => RST, D => N_03610034, Q => local_MEM_ADDR_MB3(14), SCLK => CLK, SP => N_03610036 ); I_0367611 : OFS1P3DX port map( CD => RST, D => N_03610037, Q => local_MEM_ADDR_MB3(15), SCLK => CLK, SP => N_03610039 ); I_0367612 : OFS1P3DX port map( CD => RST, D => N_03610040, Q => local_MEM_ADDR_MB3(16), SCLK => CLK, SP => N_03610042 ); I_0367613 : OFS1P3DX port map( CD => RST, D => N_03610043, Q => local_MEM_ADDR_MB3(17), SCLK => CLK, SP => N_03610045 ); I_0367615 : OFS1P3DX port map( CD => RST, D => N_0369990, Q => local_MEM_ADDR_MB3(0), SCLK => CLK, SP => N_0369993 ); I_0367617 : OFS1P3DX port map( CD => RST, D => N_0369994, Q => local_MEM_ADDR_MB3(1), SCLK => CLK, SP => N_0369996 ); I_0367618 : OFS1P3DX port map( CD => RST, D => N_0369997, Q => local_MEM_ADDR_MB3(2), SCLK => CLK, SP => N_0369999 ); I_0367619 : OFS1P3DX port map( CD => RST, D => N_03610000, Q => local_MEM_ADDR_MB3(3), SCLK => CLK, SP => N_03610002 ); I_0367620 : OFS1P3DX port map( CD => RST, D => N_03610003, Q => local_MEM_ADDR_MB3(4), SCLK => CLK, SP => N_03610005 ); I_0367621 : OFS1P3DX port map( CD => RST, D => N_03610006, Q => local_MEM_ADDR_MB3(5), SCLK => CLK, SP => N_03610008 ); I_0367833 : OFS1P3DX port map( CD => RST, D => SW_MB2_INT, Q => local_SW_MB2, SCLK => CLK, SP => N_03610258 ); I_0367834 : OFS1P3DX port map( CD => RST, D => SW_MB3_INT, Q => local_SW_MB3, SCLK => CLK, SP => N_03610260 ); I_0367836 : VHI port map( Z => N_03610258 ); I_0367837 : VHI port map( Z => N_03610260 ); I_0367839 : OFS1P3DX port map( CD => RST, D => N_03610263, Q => local_G_MB2(0), SCLK => CLK, SP => N_03610265 ); I_0367840 : OFS1P3DX port map( CD => RST, D => N_03610266, Q => local_G_MB2(1), SCLK => CLK, SP => N_03610268 ); I_0367842 : VHI port map( Z => N_03610265 ); I_0367843 : VHI port map( Z => N_03610268 ); I_0367844 : OFS1P3DX port map( CD => RST, D => N_03610269, Q => local_G_MB3(0), SCLK => CLK, SP => N_03610271 ); I_0367845 : OFS1P3DX port map( CD => RST, D => N_03610272, Q => local_G_MB3(1), SCLK => CLK, SP => N_03610274 ); I_0367846 : VHI port map( Z => N_03610271 ); I_0367847 : VHI port map( Z => N_03610274 ); I_0368759 : IFS1P3DX port map( CD => RST, D => RSFIFO_DATA(0), Q => N_03610336, SCLK => CLK, SP => N_03610282 ); I_0368760 : VHI port map( Z => N_03610282 ); I_0368763 : IFS1P3DX port map( CD => RST, D => RSFIFO_DATA(1), Q => N_03610341, SCLK => CLK, SP => N_03610288 ); I_0368764 : VHI port map( Z => N_03610288 ); I_0368767 : IFS1P3DX port map( CD => RST, D => RSFIFO_DATA(2), Q => N_03610342, SCLK => CLK, SP => N_03610294 ); I_0368768 : VHI port map( Z => N_03610294 ); I_0368771 : IFS1P3DX port map( CD => RST, D => RSFIFO_DATA(3), Q => N_03610343, SCLK => CLK, SP => N_03610300 ); I_0368772 : VHI port map( Z => N_03610300 ); I_0368775 : IFS1P3DX port map( CD => RST, D => RSFIFO_DATA(4), Q => N_03610368, SCLK => CLK, SP => N_03610349 ); I_0368776 : VHI port map( Z => N_03610349 ); I_0368779 : IFS1P3DX port map( CD => RST, D => RSFIFO_DATA(5), Q => N_03610370, SCLK => CLK, SP => N_03610351 ); I_0368780 : VHI port map( Z => N_03610351 ); I_0368783 : IFS1P3DX port map( CD => RST, D => RSFIFO_DATA(6), Q => N_03610372, SCLK => CLK, SP => N_03610353 ); I_0368784 : VHI port map( Z => N_03610353 ); I_0368787 : IFS1P3DX port map( CD => RST, D => RSFIFO_DATA(7), Q => N_03610374, SCLK => CLK, SP => N_03610355 ); I_0368788 : VHI port map( Z => N_03610355 ); I_0368791 : IFS1P3DX port map( CD => RST, D => RSFIFO_DATA(8), Q => N_03610376, SCLK => CLK, SP => N_03610357 ); I_0368792 : VHI port map( Z => N_03610357 ); I_0368795 : IFS1P3DX port map( CD => RST, D => RSFIFO_DATA(9), Q => N_03610378, SCLK => CLK, SP => N_03610359 ); I_0368796 : VHI port map( Z => N_03610359 ); I_0368799 : IFS1P3DX port map( CD => RST, D => RSFIFO_DATA(10), Q => N_03610380, SCLK => CLK, SP => N_03610361 ); I_0368800 : VHI port map( Z => N_03610361 ); I_0368803 : IFS1P3DX port map( CD => RST, D => RSFIFO_DATA(11), Q => N_03610382, SCLK => CLK, SP => N_03610363 ); I_0368804 : VHI port map( Z => N_03610363 ); I_0368806 : IFS1P3DX port map( CD => RST, D => RSFIFO_DATA(13), Q => N_03610386, SCLK => CLK, SP => N_03610367 ); I_0368808 : IFS1P3DX port map( CD => RST, D => RSFIFO_DATA(14), Q => N_03610388, SCLK => CLK, SP => N_03610306 ); I_0368809 : VHI port map( Z => N_03610306 ); I_0368812 : IFS1P3DX port map( CD => RST, D => RSFIFO_DATA(15), Q => N_03610390, SCLK => CLK, SP => N_03610312 ); I_0368813 : VHI port map( Z => N_03610312 ); I_0368817 : IFS1P3DX port map( CD => RST, D => RSFIFO_DATA(16), Q => N_03610392, SCLK => CLK, SP => N_03610318 ); I_0368818 : VHI port map( Z => N_03610318 ); I_0368821 : IFS1P3DX port map( CD => RST, D => RSFIFO_DATA(17), Q => N_03610394, SCLK => CLK, SP => N_03610324 ); I_0368822 : VHI port map( Z => N_03610324 ); I_0368827 : INV port map( A => N_03610336, Z => N_03610337 ); I_0368828 : INV port map( A => N_03610341, Z => N_03610338 ); I_0368829 : INV port map( A => N_03610342, Z => N_03610339 ); I_0368830 : INV port map( A => N_03610343, Z => N_03610340 ); I_0368835 : INV port map( A => N_03610368, Z => N_03610369 ); I_0368836 : INV port map( A => N_03610370, Z => N_03610371 ); I_0368837 : INV port map( A => N_03610372, Z => N_03610373 ); I_0368838 : INV port map( A => N_03610374, Z => N_03610375 ); I_0368839 : INV port map( A => N_03610376, Z => N_03610377 ); I_0368840 : INV port map( A => N_03610378, Z => N_03610379 ); I_0368841 : INV port map( A => N_03610380, Z => N_03610381 ); I_0368842 : INV port map( A => N_03610382, Z => N_03610383 ); I_0368843 : INV port map( A => N_03610384, Z => N_03610385 ); I_0368844 : INV port map( A => N_03610386, Z => N_03610387 ); I_0368845 : INV port map( A => N_03610388, Z => N_03610389 ); I_0368846 : INV port map( A => N_03610390, Z => N_03610391 ); I_0368850 : IFS1P3DX port map( CD => RST, D => RSFIFO_DATA(12), Q => N_03610384, SCLK => CLK, SP => N_03610365 ); I_0368851 : VHI port map( Z => N_03610365 ); I_0368853 : VHI port map( Z => N_03610367 ); I_0368854 : INV port map( A => N_03610392, Z => N_03610393 ); I_0368855 : INV port map( A => N_03610394, Z => N_03610395 ); I_0368869 : OFS1P3DX port map( CD => RST, D => rsfifo_rtb_int, Q => local_RSFIFO_RTB, SCLK => CLK, SP => N_03610421 ); I_0368870 : OFS1P3DX port map( CD => RST, D => rsfifo_mrsb_int, Q => local_RSFIFO_MRSB, SCLK => CLK, SP => N_03610422 ); I_0368872 : VHI port map( Z => N_03610421 ); I_0368873 : VHI port map( Z => N_03610422 ); I_0368874 : OFS1P3DX port map( CD => RST, D => rsfifo_oenb_int, Q => local_RSFIFO_OENB, SCLK => CLK, SP => N_03610425 ); I_0368875 : OFS1P3DX port map( CD => RST, D => rsfifo_renb_int, Q => local_RSFIFO_RENB, SCLK => CLK, SP => N_03610426 ); I_0368876 : VHI port map( Z => N_03610425 ); I_0368877 : VHI port map( Z => N_03610426 ); I_0368878 : OFS1P3DX port map( CD => RST, D => rsfifo_wenb_int, Q => local_RSFIFO_WENB, SCLK => CLK, SP => N_03610436 ); I_0368879 : VHI port map( Z => N_03610427 ); I_0368880 : IFS1P3DX port map( CD => RST, D => RSFIFO_EFB, Q => N_03610417, SCLK => CLK, SP => N_03610427 ); I_0368883 : VHI port map( Z => N_03610432 ); I_0368884 : IFS1P3DX port map( CD => RST, D => RSFIFO_FFB, Q => N_03610430, SCLK => CLK, SP => N_03610432 ); I_0368886 : VHI port map( Z => N_03610436 ); I_0368887 : INV port map( A => N_03610417, Z => rsfifo_efb_int ); I_0368888 : INV port map( A => N_03610430, Z => rsfifo_ffb_int ); I_0369090 : BMZ12FPU port map( B => MEM_DATAH_MB2(0), I => N_03610440, O => N_03610441, T => N_03610442 ); I_0369091 : VHI port map( Z => N_03610643 ); I_0369092 : VHI port map( Z => N_03610644 ); I_0369096 : BMZ12FPU port map( B => MEM_DATAH_MB2(1), I => N_03610450, O => N_03610451, T => N_03610442 ); I_0369097 : VHI port map( Z => N_03610645 ); I_0369098 : VHI port map( Z => N_03610646 ); I_0369102 : BMZ12FPU port map( B => MEM_DATAH_MB2(2), I => N_03610455, O => N_03610456, T => N_03610442 ); I_0369103 : VHI port map( Z => N_03610647 ); I_0369104 : VHI port map( Z => N_03610648 ); I_0369108 : BMZ12FPU port map( B => MEM_DATAH_MB2(3), I => N_03610460, O => N_03610461, T => N_03610442 ); I_0369109 : VHI port map( Z => N_03610649 ); I_0369110 : VHI port map( Z => N_03610650 ); I_0369114 : BMZ12FPU port map( B => MEM_DATAH_MB2(4), I => N_03610465, O => N_03610466, T => N_03610442 ); I_0369115 : VHI port map( Z => N_03610651 ); I_0369116 : VHI port map( Z => N_03610652 ); I_0369120 : BMZ12FPU port map( B => MEM_DATAH_MB2(5), I => N_03610470, O => N_03610471, T => N_03610472 ); I_0369121 : VHI port map( Z => N_03610653 ); I_0369122 : VHI port map( Z => N_03610654 ); I_0369126 : BMZ12FPU port map( B => MEM_DATAH_MB2(6), I => N_03610476, O => N_03610477, T => N_03610472 ); I_0369127 : VHI port map( Z => N_03610655 ); I_0369128 : VHI port map( Z => N_03610656 ); I_0369132 : BMZ12FPU port map( B => MEM_DATAH_MB2(7), I => N_03610481, O => N_03610482, T => N_03610472 ); I_0369133 : VHI port map( Z => N_03610657 ); I_0369134 : VHI port map( Z => N_03610658 ); I_0369138 : BMZ12FPU port map( B => MEM_DATAH_MB2(8), I => N_03610486, O => N_03610487, T => N_03610472 ); I_0369139 : VHI port map( Z => N_03610659 ); I_0369140 : VHI port map( Z => N_03610660 ); I_0369145 : BMZ12FPU port map( B => MEM_DATAL_MB2(0), I => N_03610491, O => N_03610492, T => N_03610493 ); I_0369146 : VHI port map( Z => N_03610661 ); I_0369147 : VHI port map( Z => N_03610662 ); I_0369151 : BMZ12FPU port map( B => MEM_DATAL_MB2(1), I => N_03610501, O => N_03610502, T => N_03610493 ); I_0369152 : VHI port map( Z => N_03610663 ); I_0369153 : VHI port map( Z => N_03610664 ); I_0369157 : BMZ12FPU port map( B => MEM_DATAL_MB2(2), I => N_03610506, O => N_03610507, T => N_03610493 ); I_0369158 : VHI port map( Z => N_03610665 ); I_0369159 : VHI port map( Z => N_03610666 ); I_0369163 : BMZ12FPU port map( B => MEM_DATAL_MB2(3), I => N_03610511, O => N_03610512, T => N_03610493 ); I_0369164 : VHI port map( Z => N_03610667 ); I_0369165 : VHI port map( Z => N_03610668 ); I_0369169 : BMZ12FPU port map( B => MEM_DATAL_MB2(4), I => N_03610516, O => N_03610517, T => N_03610493 ); I_0369170 : VHI port map( Z => N_03610669 ); I_0369171 : VHI port map( Z => N_03610670 ); I_0369175 : BMZ12FPU port map( B => MEM_DATAL_MB2(5), I => N_03610521, O => N_03610522, T => N_03610523 ); I_0369176 : VHI port map( Z => N_03610671 ); I_0369177 : VHI port map( Z => N_03610672 ); I_0369181 : BMZ12FPU port map( B => MEM_DATAL_MB2(6), I => N_03610527, O => N_03610528, T => N_03610523 ); I_0369182 : VHI port map( Z => N_03610673 ); I_0369183 : VHI port map( Z => N_03610674 ); I_0369187 : BMZ12FPU port map( B => MEM_DATAL_MB2(7), I => N_03610532, O => N_03610533, T => N_03610523 ); I_0369188 : VHI port map( Z => N_03610675 ); I_0369189 : VHI port map( Z => N_03610676 ); I_0369193 : BMZ12FPU port map( B => MEM_DATAL_MB2(8), I => N_03610537, O => N_03610538, T => N_03610523 ); I_0369194 : VHI port map( Z => N_03610677 ); I_0369195 : VHI port map( Z => N_03610678 ); I_0369200 : BMZ12FPU port map( B => MEM_DATAH_MB3(0), I => N_03610542, O => N_03610543, T => N_03610544 ); I_0369201 : VHI port map( Z => N_03610679 ); I_0369202 : VHI port map( Z => N_03610680 ); I_0369206 : BMZ12FPU port map( B => MEM_DATAH_MB3(1), I => N_03610552, O => N_03610553, T => N_03610544 ); I_0369207 : VHI port map( Z => N_03610681 ); I_0369208 : VHI port map( Z => N_03610682 ); I_0369212 : BMZ12FPU port map( B => MEM_DATAH_MB3(2), I => N_03610557, O => N_03610558, T => N_03610544 ); I_0369213 : VHI port map( Z => N_03610683 ); I_0369214 : VHI port map( Z => N_03610684 ); I_0369218 : BMZ12FPU port map( B => MEM_DATAH_MB3(3), I => N_03610562, O => N_03610563, T => N_03610544 ); I_0369219 : VHI port map( Z => N_03610685 ); I_0369220 : VHI port map( Z => N_03610686 ); I_0369224 : BMZ12FPU port map( B => MEM_DATAH_MB3(4), I => N_03610567, O => N_03610568, T => N_03610544 ); I_0369225 : VHI port map( Z => N_03610687 ); I_0369226 : VHI port map( Z => N_03610688 ); I_0369230 : BMZ12FPU port map( B => MEM_DATAH_MB3(5), I => N_03610572, O => N_03610573, T => N_03610574 ); I_0369231 : VHI port map( Z => N_03610689 ); I_0369232 : VHI port map( Z => N_03610690 ); I_0369236 : BMZ12FPU port map( B => MEM_DATAH_MB3(6), I => N_03610578, O => N_03610579, T => N_03610574 ); I_0369237 : VHI port map( Z => N_03610691 ); I_0369238 : VHI port map( Z => N_03610692 ); I_0369242 : BMZ12FPU port map( B => MEM_DATAH_MB3(7), I => N_03610583, O => N_03610584, T => N_03610574 ); I_0369243 : VHI port map( Z => N_03610693 ); I_0369244 : VHI port map( Z => N_03610694 ); I_0369248 : BMZ12FPU port map( B => MEM_DATAH_MB3(8), I => N_03610588, O => N_03610589, T => N_03610574 ); I_0369249 : VHI port map( Z => N_03610695 ); I_0369250 : VHI port map( Z => N_03610696 ); I_0369255 : BMZ12FPU port map( B => MEM_DATAL_MB3(0), I => N_03610593, O => N_03610594, T => N_03610595 ); I_0369256 : VHI port map( Z => N_03610697 ); I_0369257 : VHI port map( Z => N_03610698 ); I_0369261 : BMZ12FPU port map( B => MEM_DATAL_MB3(1), I => N_03610603, O => N_03610604, T => N_03610595 ); I_0369262 : VHI port map( Z => N_03610699 ); I_0369263 : VHI port map( Z => N_03610700 ); I_0369267 : BMZ12FPU port map( B => MEM_DATAL_MB3(2), I => N_03610608, O => N_03610609, T => N_03610595 ); I_0369268 : VHI port map( Z => N_03610701 ); I_0369269 : VHI port map( Z => N_03610702 ); I_0369273 : BMZ12FPU port map( B => MEM_DATAL_MB3(3), I => N_03610613, O => N_03610614, T => N_03610595 ); I_0369274 : VHI port map( Z => N_03610703 ); I_0369275 : VHI port map( Z => N_03610704 ); I_0369279 : BMZ12FPU port map( B => MEM_DATAL_MB3(4), I => N_03610618, O => N_03610619, T => N_03610595 ); I_0369280 : VHI port map( Z => N_03610705 ); I_0369281 : VHI port map( Z => N_03610706 ); I_0369285 : BMZ12FPU port map( B => MEM_DATAL_MB3(5), I => N_03610623, O => N_03610624, T => N_03610625 ); I_0369286 : VHI port map( Z => N_03610707 ); I_0369287 : VHI port map( Z => N_03610708 ); I_0369291 : BMZ12FPU port map( B => MEM_DATAL_MB3(6), I => N_03610629, O => N_03610630, T => N_03610625 ); I_0369292 : VHI port map( Z => N_03610709 ); I_0369293 : VHI port map( Z => N_03610710 ); I_0369297 : BMZ12FPU port map( B => MEM_DATAL_MB3(7), I => N_03610634, O => N_03610635, T => N_03610625 ); I_0369298 : VHI port map( Z => N_03610711 ); I_0369299 : VHI port map( Z => N_03610712 ); I_0369303 : BMZ12FPU port map( B => MEM_DATAL_MB3(8), I => N_03610639, O => N_03610640, T => N_03610625 ); I_0369304 : VHI port map( Z => N_03610713 ); I_0369305 : VHI port map( Z => N_03610714 ); I_0369310 : OFS1P3DX port map( CD => RST, D => N_03610443, Q => N_03610440, SCLK => CLK, SP => N_03610643 ); I_0369311 : IFS1P3DX port map( CD => RST, D => N_03610441, Q => N_03610445, SCLK => CLK, SP => N_03610644 ); I_0369312 : OFS1P3DX port map( CD => RST, D => N_03610452, Q => N_03610450, SCLK => CLK, SP => N_03610645 ); I_0369313 : IFS1P3DX port map( CD => RST, D => N_03610451, Q => N_03610453, SCLK => CLK, SP => N_03610646 ); I_0369314 : OFS1P3DX port map( CD => RST, D => N_03610457, Q => N_03610455, SCLK => CLK, SP => N_03610647 ); I_0369315 : IFS1P3DX port map( CD => RST, D => N_03610456, Q => N_03610458, SCLK => CLK, SP => N_03610648 ); I_0369316 : OFS1P3DX port map( CD => RST, D => N_03610462, Q => N_03610460, SCLK => CLK, SP => N_03610649 ); I_0369317 : IFS1P3DX port map( CD => RST, D => N_03610461, Q => N_03610463, SCLK => CLK, SP => N_03610650 ); I_0369318 : OFS1P3DX port map( CD => RST, D => N_03610467, Q => N_03610465, SCLK => CLK, SP => N_03610651 ); I_0369319 : IFS1P3DX port map( CD => RST, D => N_03610466, Q => N_03610468, SCLK => CLK, SP => N_03610652 ); I_0369320 : OFS1P3DX port map( CD => RST, D => N_03610473, Q => N_03610470, SCLK => CLK, SP => N_03610653 ); I_0369321 : IFS1P3DX port map( CD => RST, D => N_03610471, Q => N_03610474, SCLK => CLK, SP => N_03610654 ); I_0369322 : OFS1P3DX port map( CD => RST, D => N_03610478, Q => N_03610476, SCLK => CLK, SP => N_03610655 ); I_0369323 : IFS1P3DX port map( CD => RST, D => N_03610477, Q => N_03610479, SCLK => CLK, SP => N_03610656 ); I_0369324 : OFS1P3DX port map( CD => RST, D => N_03610483, Q => N_03610481, SCLK => CLK, SP => N_03610657 ); I_0369325 : IFS1P3DX port map( CD => RST, D => N_03610482, Q => N_03610484, SCLK => CLK, SP => N_03610658 ); I_0369326 : OFS1P3DX port map( CD => RST, D => N_03610488, Q => N_03610486, SCLK => CLK, SP => N_03610659 ); I_0369327 : IFS1P3DX port map( CD => RST, D => N_03610487, Q => N_03610489, SCLK => CLK, SP => N_03610660 ); I_0369328 : OFS1P3DX port map( CD => RST, D => N_03610495, Q => N_03610491, SCLK => CLK, SP => N_03610661 ); I_0369329 : IFS1P3DX port map( CD => RST, D => N_03610492, Q => N_03610497, SCLK => CLK, SP => N_03610662 ); I_0369330 : OFS1P3DX port map( CD => RST, D => N_03610503, Q => N_03610501, SCLK => CLK, SP => N_03610663 ); I_0369331 : IFS1P3DX port map( CD => RST, D => N_03610502, Q => N_03610504, SCLK => CLK, SP => N_03610664 ); I_0369332 : OFS1P3DX port map( CD => RST, D => N_03610508, Q => N_03610506, SCLK => CLK, SP => N_03610665 ); I_0369333 : IFS1P3DX port map( CD => RST, D => N_03610507, Q => N_03610509, SCLK => CLK, SP => N_03610666 ); I_0369334 : OFS1P3DX port map( CD => RST, D => N_03610513, Q => N_03610511, SCLK => CLK, SP => N_03610667 ); I_0369335 : IFS1P3DX port map( CD => RST, D => N_03610512, Q => N_03610514, SCLK => CLK, SP => N_03610668 ); I_0369336 : OFS1P3DX port map( CD => RST, D => N_03610518, Q => N_03610516, SCLK => CLK, SP => N_03610669 ); I_0369337 : IFS1P3DX port map( CD => RST, D => N_03610517, Q => N_03610519, SCLK => CLK, SP => N_03610670 ); I_0369338 : OFS1P3DX port map( CD => RST, D => N_03610524, Q => N_03610521, SCLK => CLK, SP => N_03610671 ); I_0369339 : IFS1P3DX port map( CD => RST, D => N_03610522, Q => N_03610525, SCLK => CLK, SP => N_03610672 ); I_0369340 : OFS1P3DX port map( CD => RST, D => N_03610529, Q => N_03610527, SCLK => CLK, SP => N_03610673 ); I_0369341 : IFS1P3DX port map( CD => RST, D => N_03610528, Q => N_03610530, SCLK => CLK, SP => N_03610674 ); I_0369342 : OFS1P3DX port map( CD => RST, D => N_03610534, Q => N_03610532, SCLK => CLK, SP => N_03610675 ); I_0369343 : IFS1P3DX port map( CD => RST, D => N_03610533, Q => N_03610535, SCLK => CLK, SP => N_03610676 ); I_0369344 : OFS1P3DX port map( CD => RST, D => N_03610539, Q => N_03610537, SCLK => CLK, SP => N_03610677 ); I_0369345 : IFS1P3DX port map( CD => RST, D => N_03610538, Q => N_03610540, SCLK => CLK, SP => N_03610678 ); I_0369346 : OFS1P3DX port map( CD => RST, D => N_03610546, Q => N_03610542, SCLK => CLK, SP => N_03610679 ); I_0369347 : IFS1P3DX port map( CD => RST, D => N_03610543, Q => N_03610548, SCLK => CLK, SP => N_03610680 ); I_0369348 : OFS1P3DX port map( CD => RST, D => N_03610554, Q => N_03610552, SCLK => CLK, SP => N_03610681 ); I_0369349 : IFS1P3DX port map( CD => RST, D => N_03610553, Q => N_03610555, SCLK => CLK, SP => N_03610682 ); I_0369350 : OFS1P3DX port map( CD => RST, D => N_03610559, Q => N_03610557, SCLK => CLK, SP => N_03610683 ); I_0369351 : IFS1P3DX port map( CD => RST, D => N_03610558, Q => N_03610560, SCLK => CLK, SP => N_03610684 ); I_0369352 : OFS1P3DX port map( CD => RST, D => N_03610564, Q => N_03610562, SCLK => CLK, SP => N_03610685 ); I_0369353 : IFS1P3DX port map( CD => RST, D => N_03610563, Q => N_03610565, SCLK => CLK, SP => N_03610686 ); I_0369354 : OFS1P3DX port map( CD => RST, D => N_03610569, Q => N_03610567, SCLK => CLK, SP => N_03610687 ); I_0369355 : IFS1P3DX port map( CD => RST, D => N_03610568, Q => N_03610570, SCLK => CLK, SP => N_03610688 ); I_0369356 : OFS1P3DX port map( CD => RST, D => N_03610575, Q => N_03610572, SCLK => CLK, SP => N_03610689 ); I_0369357 : IFS1P3DX port map( CD => RST, D => N_03610573, Q => N_03610576, SCLK => CLK, SP => N_03610690 ); I_0369358 : OFS1P3DX port map( CD => RST, D => N_03610580, Q => N_03610578, SCLK => CLK, SP => N_03610691 ); I_0369359 : IFS1P3DX port map( CD => RST, D => N_03610579, Q => N_03610581, SCLK => CLK, SP => N_03610692 ); I_0369360 : OFS1P3DX port map( CD => RST, D => N_03610585, Q => N_03610583, SCLK => CLK, SP => N_03610693 ); I_0369361 : IFS1P3DX port map( CD => RST, D => N_03610584, Q => N_03610586, SCLK => CLK, SP => N_03610694 ); I_0369362 : OFS1P3DX port map( CD => RST, D => N_03610590, Q => N_03610588, SCLK => CLK, SP => N_03610695 ); I_0369363 : IFS1P3DX port map( CD => RST, D => N_03610589, Q => N_03610591, SCLK => CLK, SP => N_03610696 ); I_0369364 : OFS1P3DX port map( CD => RST, D => N_03610597, Q => N_03610593, SCLK => CLK, SP => N_03610697 ); I_0369365 : IFS1P3DX port map( CD => RST, D => N_03610594, Q => N_03610599, SCLK => CLK, SP => N_03610698 ); I_0369366 : OFS1P3DX port map( CD => RST, D => N_03610605, Q => N_03610603, SCLK => CLK, SP => N_03610699 ); I_0369367 : IFS1P3DX port map( CD => RST, D => N_03610604, Q => N_03610606, SCLK => CLK, SP => N_03610700 ); I_0369368 : OFS1P3DX port map( CD => RST, D => N_03610610, Q => N_03610608, SCLK => CLK, SP => N_03610701 ); I_0369369 : IFS1P3DX port map( CD => RST, D => N_03610609, Q => N_03610611, SCLK => CLK, SP => N_03610702 ); I_0369370 : OFS1P3DX port map( CD => RST, D => N_03610615, Q => N_03610613, SCLK => CLK, SP => N_03610703 ); I_0369371 : IFS1P3DX port map( CD => RST, D => N_03610614, Q => N_03610616, SCLK => CLK, SP => N_03610704 ); I_0369372 : OFS1P3DX port map( CD => RST, D => N_03610620, Q => N_03610618, SCLK => CLK, SP => N_03610705 ); I_0369373 : IFS1P3DX port map( CD => RST, D => N_03610619, Q => N_03610621, SCLK => CLK, SP => N_03610706 ); I_0369374 : OFS1P3DX port map( CD => RST, D => N_03610626, Q => N_03610623, SCLK => CLK, SP => N_03610707 ); I_0369375 : IFS1P3DX port map( CD => RST, D => N_03610624, Q => N_03610627, SCLK => CLK, SP => N_03610708 ); I_0369376 : OFS1P3DX port map( CD => RST, D => N_03610631, Q => N_03610629, SCLK => CLK, SP => N_03610709 ); I_0369377 : IFS1P3DX port map( CD => RST, D => N_03610630, Q => N_03610632, SCLK => CLK, SP => N_03610710 ); I_0369378 : OFS1P3DX port map( CD => RST, D => N_03610636, Q => N_03610634, SCLK => CLK, SP => N_03610711 ); I_0369379 : IFS1P3DX port map( CD => RST, D => N_03610635, Q => N_03610637, SCLK => CLK, SP => N_03610712 ); I_0369380 : OFS1P3DX port map( CD => RST, D => N_03610641, Q => N_03610639, SCLK => CLK, SP => N_03610713 ); I_0369381 : IFS1P3DX port map( CD => RST, D => N_03610640, Q => N_03610642, SCLK => CLK, SP => N_03610714 ); I_03695 : vme_decoder port map( BASE_ADDRESS(7 downto 0) => N_03615681(7 downto 0), BOARD_ADDR(7 downto 0) => BOARD_ADDR(7 downto 0), CLK => CLK, CLK_LOAD => N_03614218, CLK_M(8 downto 0) => N_03635(8 downto 0), CLK_N(1 downto 0) => N_03625(1 downto 0), CLK_T(2 downto 0) => N_03614221(2 downto 0), COMMAND(3 downto 0) => N_03615276(3 downto 0), COMMAND_DATA(31 downto 0) => N_03614456(31 downto 0), DIFFERENCE_FOUND => N_03613730, EXECUTE_COMMAND => N_03613484, HISTOGRAMMING_BUSY => N_03613950, HISTO_BLOCK_BUSY => N_03616492, HISTO_MEM_CLEAR => N_03613943, HISTO_MEM_DATA_IN(31 downto 0) => N_03613044(31 downto 0), HISTO_MEM_READ => N_03612318, LADDR(31 downto 1) => LADDR(31 downto 1), LAST_COMMAND(4 downto 0) => N_03614249(4 downto 0), LDATA(31 downto 0) => LDATA(31 downto 0), LOAD_BASE_ADDRESS => N_03614231, RESYNC_FIFO_DATA(17 downto 0) => N_03613741(17 downto 0), RSFIFO_READ => N_03614454, RSFIFO_RETRANSMIT => N_03614453, RST => RST, SIM_MEM_CNT_RST => N_03613946, SIM_MEM_WRITE => N_03613043, START_HISTOGRAMMING => N_03614240, START_SENDING_TV => N_03614241, SVIC_CS(5 downto 0) => SVIC_CS(5 downto 0), SVIC_DBE(3 downto 0) => SVIC_DBE(3 downto 0), SVIC_LACK_N => local_SVIC_LACK_N, SVIC_LDEN_N => SVIC_LDEN_N, SVIC_LDS => SVIC_LDS, SVIC_LIRQ => local_SVIC_LIRQ, SVIC_PREN_N => SVIC_PREN_N, SVIC_REGION(3 downto 0) => local_SVIC_REGION(3 downto 0), SVIC_R_W => SVIC_R_W, SVIC_STROBE => SVIC_STROBE, SVIC_SWDEN_N => SVIC_SWDEN_N, TV_MEM_CNT_RST => N_03613046, TV_MEM_WRITE => N_03613737, TV_OR_SIM_DATA(17 downto 0) => N_03613053(17 downto 0), TV_RUNNING => N_03614248, VALID_VME_ACCESS => N_03614455, VCOMP(3 downto 0) => VCOMP(3 downto 0), VME_XCVR_LDS => local_VME_XCVR_LDS, VME_XCVR_MWB_N => local_VME_XCVR_MWB_N, VME_XCVR_STROBE_N => local_VME_XCVR_STROBE_N ); I_0369642 : serialtoparallel port map( bc(7 downto 0) => N_03612741(7 downto 0), channel(6 downto 0) => DI_A(10 downto 4), chip(3 downto 0) => DI_A(3 downto 0), clk => CLK, l1t(3 downto 0) => N_03612744(3 downto 0), rst => RST, serial_data => rsfifo_data_int(0), write => write_A ); I_0369652 : serialtoparallel port map( bc(7 downto 0) => N_03614870(7 downto 0), channel(6 downto 0) => DI_B(10 downto 4), chip(3 downto 0) => DI_B(3 downto 0), clk => CLK, l1t(3 downto 0) => N_03614871(3 downto 0), rst => RST, serial_data => rsfifo_data_int(1), write => write_B ); I_0369857 : outfifo_contr port map( busy_int => N_03613713, clk => CLK, cmd_stream => N_03613476, data(17 downto 0) => FIFO_OUT_INT(17 downto 0), efb => outfifo_efB_int, ffb => outfifo_ffB_int, mem_data(17 downto 0) => N_03613714(17 downto 0), mrsb => outfifo_mrsB_int, oenb => outfifo_oenB_int, renb => outfifo_renB_int, reset_fifo_int => N_03613715, rst => RST, rtb => outfifo_rtB_int, send_fifo_int => N_03613511, send_stream => N_03613485, wenb => outfifo_wenB_int, write_mem_data_to_fifo => N_03613717 ); -- FRAMES end rtl; LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.all; entity vme_decoder is port( BASE_ADDRESS : out std_logic_vector(7 downto 0); BOARD_ADDR : in std_logic_vector(7 downto 0); CLK : in std_logic; COMMAND : out std_logic_vector(3 downto 0); COMMAND_DATA : out std_logic_vector(31 downto 0); DIFFERENCE_FOUND : in std_logic; HISTOGRAMMING_BUSY : in std_logic; HISTO_BLOCK_BUSY : in std_logic; HISTO_MEM_DATA_IN : in std_logic_vector(31 downto 0); LADDR : in std_logic_vector(31 downto 1); RESYNC_FIFO_DATA : in std_logic_vector(17 downto 0); RST : in std_logic; SVIC_CS : in std_logic_vector(5 downto 0); SVIC_DBE : in std_logic_vector(3 downto 0); SVIC_LDEN_N : in std_logic; SVIC_LDS : in std_logic; SVIC_PREN_N : in std_logic; SVIC_R_W : in std_logic; SVIC_STROBE : in std_logic; SVIC_SWDEN_N : in std_logic; TV_OR_SIM_DATA : out std_logic_vector(17 downto 0); TV_RUNNING : in std_logic; VCOMP : in std_logic_vector(3 downto 0); CLK_LOAD : out std_logic; CLK_M : out std_logic_vector(8 downto 0); CLK_N : out std_logic_vector(1 downto 0); CLK_T : out std_logic_vector(2 downto 0); EXECUTE_COMMAND : out std_logic; HISTO_MEM_CLEAR : out std_logic; HISTO_MEM_READ : out std_logic; LAST_COMMAND : out std_logic_vector(4 downto 0); LOAD_BASE_ADDRESS : out std_logic; RSFIFO_READ : out std_logic; RSFIFO_RETRANSMIT : out std_logic; SIM_MEM_CNT_RST : out std_logic; SIM_MEM_WRITE : out std_logic; START_HISTOGRAMMING : out std_logic; START_SENDING_TV : out std_logic; SVIC_LACK_N : out std_logic; SVIC_LIRQ : out std_logic; SVIC_REGION : out std_logic_vector(3 downto 0); TV_MEM_CNT_RST : out std_logic; TV_MEM_WRITE : out std_logic; VALID_VME_ACCESS : out std_logic; VME_XCVR_LDS : out std_logic; VME_XCVR_MWB_N : out std_logic; VME_XCVR_STROBE_N : out std_logic; LDATA : inout std_logic_vector(31 downto 0) ); end vme_decoder; architecture structure of vme_decoder is type state_type is (sm_idle,startup,decode,rd_acc_st,wr_acc_st,acknowledge,wait_for_done); signal state,decode_this : state_type; signal vme_startup_done : std_logic; signal dbus_oe : std_logic_vector(3 downto 0); signal valid_access,valid_access_tmp,valid_access_strobe : std_logic; signal startup_cntr : unsigned(4 downto 0); signal write_access : std_logic; signal cmd1,cmd2,cmd3,cmd4 : std_logic_vector(4 downto 0); signal vme_xcvr_lds_i : std_logic; signal cs,dbe : std_logic; signal tv_run_int : std_logic; signal dbus_in,dbus_out : std_logic_vector(31 downto 0); begin SVIC_REGION(3) <= '0'; SVIC_REGION(2) <= not VCOMP(3); SVIC_REGION(1) <= not VCOMP(2); SVIC_REGION(0) <= not VCOMP(1); SVIC_LIRQ <= '1'; VME_XCVR_MWB_N <= '1'; COMMAND <= cmd1(3 downto 0); LAST_COMMAND <= cmd1(4 downto 0); VALID_VME_ACCESS <= valid_access_strobe; resync : process (CLK,RST) begin -- resync if (RST='1') then dbus_in <= (others => '0'); elsif (CLK'event and CLK='1') then if (valid_access_strobe='1') then dbus_in <= LDATA; else dbus_in <= dbus_in; end if; end if; end process resync; input_data : process (CLK,RST) begin -- input_data if (RST='1') then BASE_ADDRESS <= (others => '0'); CLK_M <= (others => '0'); CLK_N <= (others => '0'); CLK_T <= (others => '0'); TV_OR_SIM_DATA <= (others => '0'); COMMAND_DATA <= (others => '0'); elsif (CLK'event and CLK='1') then BASE_ADDRESS <= dbus_in(7 downto 0); CLK_M <= dbus_in(8 downto 0); CLK_N <= dbus_in(10 downto 9); CLK_T <= dbus_in(13 downto 11); TV_OR_SIM_DATA <= dbus_in(17 downto 0); COMMAND_DATA <= dbus_in; end if; end process input_data; output_data : process (CLK,RST) begin -- output_data if (RST='1') then dbus_out <= (others => '0'); elsif (CLK'event and CLK='1') then dbus_out(31 downto 18) <= HISTO_MEM_DATA_IN(31 downto 18); if (cmd2="00100") then dbus_out(17 downto 0) <= HISTO_MEM_DATA_IN(17 downto 0); elsif (cmd2="01101") then dbus_out(17 downto 0) <= RESYNC_FIFO_DATA(17 downto 0); elsif (cmd2="00000") then -- read status reg dbus_out(16) <= HISTOGRAMMING_BUSY or tv_run_int or HISTO_BLOCK_BUSY; dbus_out(15 downto 0) <= "1111101011001110"; dbus_out(17) <= '0'; end if; end if; end process output_data; databus_tristate : process (dbus_oe, dbus_out) begin -- databus_tristate if (dbus_oe(1)='1') then LDATA(7 downto 0) <= dbus_out(7 downto 0); else LDATA(7 downto 0) <= "ZZZZZZZZ"; end if; if (dbus_oe(2)='1') then LDATA(15 downto 8) <= dbus_out(15 downto 8); else LDATA(15 downto 8) <= "ZZZZZZZZ"; end if; if (dbus_oe(3)='1') then LDATA(23 downto 16) <= dbus_out(23 downto 16); else LDATA(23 downto 16) <= "ZZZZZZZZ"; end if; if (dbus_oe(0)='1') then LDATA(31 downto 24) <= dbus_out(31 downto 24); else LDATA(31 downto 24) <= "ZZZZZZZZ"; end if; end process databus_tristate; lds_mux : process (vme_startup_done,SVIC_LDS,vme_xcvr_lds_i) begin -- lds_mux if (vme_startup_done='0') then VME_XCVR_LDS <= vme_xcvr_lds_i; else VME_XCVR_LDS <= SVIC_LDS; end if; end process lds_mux; sync : process (CLK,RST) begin -- sync if (RST='1') then valid_access <= '0'; valid_access_tmp <= '0'; valid_access_strobe <= '0'; cs <= '0'; dbe <= '0'; vme_xcvr_lds_i <= '1'; decode_this <= sm_idle; tv_run_int <= '0'; elsif (CLK'event and CLK='1') then tv_run_int <= TV_RUNNING; decode_this <= state; vme_xcvr_lds_i <= not std_logic(startup_cntr(3)); if (SVIC_CS="000000") then cs <= '0'; else cs <= '1'; end if; if (SVIC_DBE="0000") then dbe <= '0'; else dbe <= '1'; end if; if (cs='1' and dbe='1') then valid_access_tmp <= '1'; else valid_access_tmp <= '0'; end if; if (valid_access_tmp='1' and cs='1' and dbe='1') then valid_access <= '1'; else valid_access <= '0'; end if; if (valid_access='0' and valid_access_tmp='1' and cs='1' and dbe='1') then valid_access_strobe <= '1'; else valid_access_strobe <= '0'; end if; if (valid_access_strobe='1') then cmd1 <= LADDR(8 downto 4); cmd2 <= LADDR(8 downto 4); cmd3 <= LADDR(8 downto 4); cmd4 <= LADDR(8 downto 4); write_access <= not SVIC_R_W; else cmd1 <= cmd1; cmd2 <= cmd2; cmd3 <= cmd3; cmd4 <= cmd4; write_access <= not SVIC_R_W; end if; end if; end process sync; decode_process : process (CLK,RST) begin if (RST='1') then vme_startup_done <= '0'; startup_cntr <= "00000"; state <= sm_idle; dbus_oe <= "0000"; elsif (CLK'event and CLK='1') then case state is when sm_idle => dbus_oe <= "0000"; if (vme_startup_done='0') then state <= startup; elsif (valid_access='1') then state <= decode; else state <= sm_idle; end if; when startup => dbus_oe <= "1111"; startup_cntr <= startup_cntr + "00001"; if (std_logic_vector(startup_cntr)="11111") then state <= sm_idle; vme_startup_done <= '1'; dbus_oe <= "0000"; else state <= startup; end if; when decode => if (write_access='1') then state <= wr_acc_st; else state <= rd_acc_st; end if; when wr_acc_st => state <= acknowledge; when rd_acc_st => dbus_oe <= "1111"; state <= acknowledge; when acknowledge => state <= wait_for_done; when wait_for_done => if (valid_access='0') then state <= sm_idle; dbus_oe <= "0000"; else state <= wait_for_done; end if; when others => state <= acknowledge; end case; -- state end if; end process decode_process; parallel_decoded_signal : process (CLK,RST) begin -- parallel_decoded_signal if (RST='1') then SIM_MEM_CNT_RST <= '0'; TV_MEM_CNT_RST <= '0'; HISTO_MEM_CLEAR <= '0'; EXECUTE_COMMAND <= '0'; START_HISTOGRAMMING <= '0'; START_SENDING_TV <= '0'; CLK_LOAD <= '0'; HISTO_MEM_READ <= '0'; LOAD_BASE_ADDRESS <= '0'; SIM_MEM_WRITE <= '0'; TV_MEM_WRITE <= '0'; RSFIFO_RETRANSMIT <= '0'; RSFIFO_READ <= '0'; SVIC_LACK_N <= '1'; elsif (CLK'event and CLK='1') then if (decode_this=wait_for_done) then SVIC_LACK_N <= '0'; else SVIC_LACK_N <= '1'; end if; if (decode_this=rd_acc_st and cmd3="00100") then HISTO_MEM_READ <= '1'; else HISTO_MEM_READ <= '0'; end if; if (decode_this=rd_acc_st and cmd3="01101") then RSFIFO_READ <= '1'; else RSFIFO_READ <= '0'; end if; if (decode_this=wr_acc_st and cmd3="01001") then RSFIFO_RETRANSMIT <= '1'; else RSFIFO_RETRANSMIT <= '0'; end if; if (decode_this=wr_acc_st and cmd3="00111") then TV_MEM_WRITE <= '1'; else TV_MEM_WRITE <= '0'; end if; if (decode_this=wr_acc_st and cmd3="01000") then SIM_MEM_WRITE <= '1'; else SIM_MEM_WRITE <= '0'; end if; if (decode_this=wr_acc_st and cmd3="00101") then LOAD_BASE_ADDRESS <= '1'; else LOAD_BASE_ADDRESS <= '0'; end if; if (decode_this=wr_acc_st and cmd4="01111") then CLK_LOAD <= '1'; else CLK_LOAD <= '0'; end if; if (decode_this=wr_acc_st and cmd4="00110") then START_SENDING_TV <= '1'; else START_SENDING_TV <= '0'; end if; if (decode_this=wr_acc_st and cmd4="01110") then START_HISTOGRAMMING <= '1'; else START_HISTOGRAMMING <= '0'; end if; if (decode_this=wr_acc_st and cmd4="00011") then HISTO_MEM_CLEAR <= '1'; else HISTO_MEM_CLEAR <= '0'; end if; if (decode_this=wr_acc_st and cmd4="00010") then SIM_MEM_CNT_RST <= '1'; else SIM_MEM_CNT_RST <= '0'; end if; if (decode_this=wr_acc_st and cmd4="00001") then TV_MEM_CNT_RST <= '1'; else TV_MEM_CNT_RST <= '0'; end if; if (decode_this=wr_acc_st and cmd4(4)='1') then EXECUTE_COMMAND <= '1'; else EXECUTE_COMMAND <= '0'; end if; end if; end process parallel_decoded_signal; end structure; LIBRARY ieee; USE ieee.std_logic_1164.ALL; --use ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.ALL; entity clk_loader is port( CLK : in std_logic; CLK_LOAD : in std_logic; M : in std_logic_vector(8 downto 0); N : in std_logic_vector(1 downto 0); T : in std_logic_vector(2 downto 0); RST : in std_logic; clk_test : in std_logic; clk_data : out std_logic; -- not used clk_ld : out std_logic; clk_ld_clk : out std_logic ); end clk_loader; architecture structure of clk_loader is signal local_clk_ld_clk : std_logic; signal data_sr : std_logic_vector(13 downto 0); signal ld_sr : std_logic_vector(15 downto 0); signal divide_cnt : std_logic_vector(2 downto 0); signal divide_cnt_rst : std_logic; signal do_shift : std_logic_vector(1 downto 0); begin output_regs : process (CLK,RST) begin -- output_regs if (RST='1') then clk_data <= '0'; clk_ld <= '0'; clk_ld_clk <= '0'; elsif (CLK'event and CLK='1') then clk_data <= data_sr(13); clk_ld <= ld_sr(15) and not ld_sr(14); clk_ld_clk <= local_clk_ld_clk and ld_sr(13); end if; end process output_regs; data_shift_reg : process (CLK,RST) begin -- data_shift_reg if (RST='1') then data_sr <= (others => '0'); elsif (CLK'event and CLK='1') then if (CLK_LOAD='1') then data_sr(13 downto 11) <= T(2 downto 0); data_sr(10 downto 9) <= N(1 downto 0); data_sr(8 downto 0) <= M(8 downto 0); elsif (do_shift(0)='1') then data_sr(13 downto 1) <= data_sr(12 downto 0); data_sr(0) <= '0'; else data_sr <= data_sr; end if; end if; end process data_shift_reg; ld_shift_reg : process (CLK,RST) begin -- ld_shift_reg if (RST='1') then ld_sr <= (others => '0'); elsif (CLK'event and CLK='1') then if (CLK_LOAD='1') then ld_sr <= (others => '1'); elsif (do_shift(1)='1') then ld_sr(15 downto 1) <= ld_sr(14 downto 0); ld_sr(0) <= '0'; else ld_sr <= ld_sr; end if; end if; end process ld_shift_reg; counter_control : process (CLK,RST) begin -- counter_control if (RST='1') then divide_cnt_rst <= '0'; elsif (CLK'event and CLK='1') then if (CLK_LOAD='1') then divide_cnt_rst <= '1'; else divide_cnt_rst <= '0'; end if; end if; end process counter_control; divide_counter : process (CLK,RST) begin -- if (RST='1') then divide_cnt <= "000"; do_shift <= (others => '0'); local_clk_ld_clk <= '0'; elsif (CLK'event and CLK='1') then if (divide_cnt_rst='1') then divide_cnt <= (others => '0'); local_clk_ld_clk <= '0'; do_shift <= (others => '0'); else divide_cnt <= divide_cnt + "001"; local_clk_ld_clk <= divide_cnt(2) and ld_sr(15); do_shift <= (others => (local_clk_ld_clk and (not divide_cnt(2)))); end if; end if; end process divide_counter; end structure; LIBRARY ieee; USE ieee.std_logic_1164.ALL; entity outfifo_contr is port( clk : in std_logic; rst : in std_logic; cmd_stream : in std_logic; efb : in std_logic; ffb : in std_logic; mem_data : in std_logic_vector(17 downto 0); reset_fifo_int : in std_logic; send_fifo_int : in std_logic; send_stream : in std_logic; write_mem_data_to_fifo : in std_logic; busy_int : out std_logic; data : out std_logic_vector(17 downto 0); mrsb : out std_logic; oenb : out std_logic; renb : out std_logic; rtb : out std_logic; wenb : out std_logic ); end outfifo_contr; architecture structure of outfifo_contr is type StateType is (idle,rst_fifo,send_command); signal state : StateType; signal send,send_1,send_2,send_3 : std_logic; signal sr : std_logic_vector(3 downto 0); begin data(17 downto 1) <= "00000000000000000"; oenb <= '0'; rtb <= '1'; ff : process (CLK,RST) begin -- ff if (RST='1') then mrsb <= '0'; send <= '0'; send_1 <= '0'; send_2 <= '0'; send_3 <= '0'; sr <= (others => '0'); elsif (CLK'event and CLK='1') then sr(3 downto 1) <= sr(2 downto 0); sr(0) <= cmd_stream; data(0) <= sr(3); if (state=rst_fifo) then mrsb <= '0'; else mrsb <= '1'; end if; if (state=send_command) then send <= '1'; else send <= '0'; end if; send_1 <= send; send_2 <= send_1; send_3 <= send_2; if (send='1') then wenb <= '0'; else wenb <= '1'; end if; if (send_3='1') then renb <= '0'; else renb <= '1'; end if; end if; end process ff; sm : process (CLK,RST) begin -- sm if (RST='1') then state <= idle; elsif (CLK'event and CLK='1') then case state is when idle => if (send_stream='1') then state <= rst_fifo; else state <= idle; end if; when rst_fifo => state <= send_command; when send_command => if (send_stream='1') then state <= send_command; else state <= idle; end if; when others => state <= idle; end case; end if; end process sm; end structure; LIBRARY ieee; USE ieee.std_logic_1164.ALL; entity resync_fifo_contr is port( clk : in std_logic; rst : in std_logic; efb : in std_logic; ffb : in std_logic; read : in std_logic; read_TV_data : in std_logic; receive_TV_data : in std_logic; receive_data : in std_logic; reset_fifo : in std_logic; reset_fifo_2 : in std_logic; retransmit : in std_logic; mrsb : out std_logic; oenb : out std_logic; renb : out std_logic; rtb : out std_logic; vme_data : out std_logic_vector(17 downto 0); wenb : out std_logic ); end resync_fifo_contr; architecture structure of resync_fifo_contr is signal rd1,rd2 : std_logic; begin oenb <= '0'; rtb <= '1'; vme_data <= (others => '0'); ff : process (CLK,RST) begin -- ff if (RST='1') then mrsb <= '0'; renb <= '1'; wenb <= '1'; rd1 <= '0'; rd2 <= '0'; elsif (CLK'event and CLK='1') then mrsb <= reset_fifo; wenb <= not receive_data; rd1 <= receive_data; rd2 <= rd1; renb <= not rd2; end if; end process ff; end structure; LIBRARY ieee; USE ieee.std_logic_1164.ALL; entity histo_controller is port( CLK : in std_logic; RST : in std_logic; BUSY_IN : in std_logic; START : in std_logic; BUSY : out std_logic; SEND_TRIGGERS : out std_logic; STOP_HIST : out std_logic; STRT_HIST : out std_logic; receive_data : out std_logic; reset_resync_fifo : out std_logic ); end histo_controller; architecture structure of histo_controller is type StateType is (idle,start_st,w0,w1,w2,wait_til_done,end_hist); signal state : StateType; signal receive_data_int,stop_hist_int : std_logic; signal busy_int : std_logic; begin RECEIVE_DATA <= receive_data_int; STOP_HIST <= stop_hist_int; BUSY <= BUSY_IN or busy_int; out_regs : process (CLK,RST) begin -- out_regs if (RST='1') then busy_int <= '0'; SEND_TRIGGERS <= '0'; STRT_HIST <= '0'; receive_data_INT <= '0'; reset_resync_fifo <= '0'; elsif (CLK='1' and CLK'event) then if (state=start_st) then stop_hist_int <= '0'; receive_data_INT <= '1'; elsif (state=end_hist) then stop_hist_int <= '1'; receive_data_INT <= '0'; else receive_data_INT <= receive_data_INT; stop_hist_int <= stop_hist_int; end if; if (state=idle) then busy_int <= '0'; else busy_int <= '1'; end if; if (state=start_st) then SEND_TRIGGERS <= '1'; STRT_HIST <= '1'; reset_resync_fifo <= '1'; else SEND_TRIGGERS <= '0'; STRT_HIST <= '0'; reset_resync_fifo <= '1'; end if; end if; end process out_regs; sm : process (CLK,RST) begin -- sm if (RST='1') then state <= idle; elsif (CLK'event and CLK='1') then case state is when idle => if (START='1') then state <= start_st; else state <= idle; end if; when start_st => state <= w0; when w0 => state <= w1; when w1 => state <= w2; when w2 => state <= wait_til_done; when wait_til_done => if (BUSY_IN='1') then state <= wait_til_done; else state <= end_hist; end if; when end_hist => state <= idle; when others => state <= idle; end case; end if; end process sm; end structure; LIBRARY ieee; USE ieee.std_logic_1164.ALL; use ieee.std_logic_arith.all; entity com_generator is port( clk : in std_logic; rst : in std_logic; command : in std_logic_vector(3 downto 0); data : in std_logic_vector(31 downto 0); execute : in std_logic; send_triggers : in std_logic; bitstream : out std_logic; busy : out std_logic; send_stream : out std_logic ); end com_generator; architecture structure of com_generator is type StateType is (idle_st,ld_cnt_st,send_trig_st,wait_st,end_dec_st); type StateType2 is (idle_state,send_str_state,wait_state,send_tr_state); signal state : StateType; signal sm_state : StateType2; signal set_trigger_delay : std_logic; signal load_num_triggers : std_logic; signal send_soft_reset : std_logic; signal send_bc_reset : std_logic; signal write_config_reg : std_logic; signal reset_mask_reg_pointer : std_logic; signal write_mask_reg : std_logic; signal send_mask_reg : std_logic; signal write_strobe_delay_reg : std_logic; signal write_threshold_reg : std_logic; signal enable_data_taking : std_logic; signal enable_int_strobe : std_logic; signal disable_int_strobe : std_logic; signal load_bias_dac : std_logic; signal load_trim_dac : std_logic; signal chip_address : std_logic_vector(5 downto 0); signal command_demux : std_logic_vector(15 downto 0); signal soft_reset : std_logic_vector(6 downto 0); signal bc_reset : std_logic_vector(6 downto 0); signal enable_data_taking_reg : std_logic_vector(26 downto 0); signal trigger_delay : std_logic_vector(15 downto 0); signal num_triggers : std_logic_vector(15 downto 0); signal internal_strobe_enabled : std_logic; signal config_reg : std_logic_vector(42 downto 0); signal strobe_delay_reg : std_logic_vector(42 downto 0); signal threshold_reg : std_logic_vector(42 downto 0); signal bias_dac_reg : std_logic_vector(42 downto 0); signal trim_dac_reg : std_logic_vector(42 downto 0); signal mask_reg_pointer : unsigned(1 downto 0); signal mask_0,mask_1,mask_2,mask_3 : std_logic_vector(31 downto 0); signal mask_reg : std_logic_vector(154 downto 0); signal busy_counter : unsigned(7 downto 0); signal start_signal : std_logic; signal busy_int : std_logic; signal trigger_cnt : unsigned(15 downto 0); signal wait_cnt : unsigned(15 downto 0); signal send_1_trig : std_logic; signal sm_busy : std_logic; signal cc_counter : unsigned(7 downto 0); signal cc_counter_reg : std_logic_vector(7 downto 0); signal load_cc_counter : std_logic; signal issue_pulse_reg : std_logic_vector(26 downto 0); signal trig_signal_reg : std_logic_vector(2 downto 0); signal trig_busy,tb3,tb2,tb1,tb0 : std_logic; begin busy <= busy_int or sm_busy or trig_busy; send_stream <= busy_int or sm_busy; with state select send_1_trig <= '1' when send_trig_st, '0' when others; with command select command_demux <= "0000000000000001" when "0000", "0000000000000010" when "0001", "0000000000000100" when "0010", "0000000000001000" when "0011", "0000000000010000" when "0100", "0000000000100000" when "0101", "0000000001000000" when "0110", "0000000010000000" when "0111", "0000000100000000" when "1000", "0000001000000000" when "1001", "0000010000000000" when "1010", "0000100000000000" when "1011", "0001000000000000" when "1100", "0010000000000000" when "1101", "0100000000000000" when "1110", "1000000000000000" when others; sm : process (CLK,RST) begin -- sm if (RST='1') then state <= idle_st; elsif (CLK'event and CLK='1') then case state is when idle_st => if (send_triggers='1' and not (std_logic_vector(num_triggers)="0000000000000000")) then state <= ld_cnt_st; else state <= idle_st; end if; when ld_cnt_st => state <= send_trig_st; when send_trig_st => state <= wait_st; when wait_st => if (std_logic_vector(wait_cnt)="0000000000000000") then state <= end_dec_st; else state <= wait_st; end if; when end_dec_st => if (std_logic_vector(trigger_cnt)="0000000000000000") then state <= idle_st; else state <= send_trig_st; end if; when others => state <= idle_st; end case; end if; end process sm; sm2 : process (CLK,RST) begin -- sm2 if (RST='1') then sm_state <= idle_state; elsif (CLK'event and CLK='1') then case sm_state is when idle_state => if (send_1_trig='1') then sm_state <= send_str_state; else sm_state <= idle_state; end if; when send_str_state => sm_state <= wait_state; when wait_state => if (std_logic_vector(cc_counter)="00000000") then sm_state <= send_tr_state; else sm_state <= wait_state; end if; when send_tr_state => sm_state <= idle_state; when others => sm_state <= idle_state; end case; end if; end process sm2; cc_counter_process : process (CLK,RST) begin -- cc_counter_process if (RST='1') then cc_counter <= (others => '0'); elsif (CLK'event and CLK='1') then if (sm_state=send_str_state) then cc_counter <= unsigned(cc_counter_reg); elsif (sm_state=wait_state) then cc_counter <= cc_counter - 1; end if; end if; end process cc_counter_process; load_cc_counter_process : process (CLK,RST) begin -- load_cc_counter_process if (RST='1') then cc_counter_reg <= (others => '0'); elsif (CLK'event and CLK='1') then if (load_cc_counter='1') then cc_counter_reg <= data(7 downto 0); else cc_counter_reg <= cc_counter_reg; end if; end if; end process load_cc_counter_process; issue_pulse_process : process (CLK,RST) begin -- issue_pulse_process if (RST='1') then issue_pulse_reg <= (others => '0'); elsif (CLK'event and CLK='1') then if (sm_state=send_str_state) then issue_pulse_reg(26 downto 20) <= "1010111"; issue_pulse_reg(19 downto 12) <= "00001100"; issue_pulse_reg(11 downto 6) <= chip_address; issue_pulse_reg(5 downto 0) <= "110000"; else issue_pulse_reg(0) <= '0'; issue_pulse_reg(26 downto 1) <= issue_pulse_reg(25 downto 0); end if; end if; end process issue_pulse_process; trigger_busy_process : process (CLK,RST) begin -- trigger_busy_process if (RST='1') then tb3 <= '0'; tb2 <= '0'; tb1 <= '0'; tb0 <= '0'; trig_busy <= '0'; elsif (CLK'event and CLK='1') then if (sm_state=send_str_state) then tb3 <= '1'; elsif (sm_state=send_tr_state) then tb3 <= '0'; else tb3 <= tb3; end if; tb2 <= tb3; tb1 <= tb2; tb0 <= tb1; trig_busy <= tb3 or tb2 or tb1 or tb0; end if; end process trigger_busy_process; send_trigger_process : process (CLK,RST) begin -- send_trigger_process if (RST='1') then trig_signal_reg <= (others => '0'); elsif (CLK'event and CLK='1') then if (sm_state=send_tr_state) then trig_signal_reg <= "110"; else trig_signal_reg(0) <= '0'; trig_signal_reg(2 downto 1) <= trig_signal_reg(1 downto 0); end if; end if; end process send_trigger_process; trigger_cnt_process : process (CLK,RST) begin -- trigger_cnt_process if (RST='1') then trigger_cnt <= (others => '0'); elsif (CLK'event and CLK='1') then if (state=ld_cnt_st) then trigger_cnt <= unsigned(num_triggers); elsif (state=send_trig_st) then trigger_cnt <= trigger_cnt - 1; end if; end if; end process trigger_cnt_process; wait_cnt_process : process (CLK,RST) begin -- wait_cnt_process if (RST='1') then elsif (CLK'event and CLK='1') then if (state=send_trig_st) then wait_cnt <= unsigned(trigger_delay); elsif (state=wait_st) then wait_cnt <= wait_cnt - 1; end if; end if; end process wait_cnt_process; latch_command : process (CLK,RST) begin -- latch_command if (RST='1') then set_trigger_delay <= '0'; load_num_triggers <= '0'; send_soft_reset <= '0'; send_bc_reset <= '0'; write_config_reg <= '0'; reset_mask_reg_pointer <= '0'; write_mask_reg <= '0'; send_mask_reg <= '0'; write_strobe_delay_reg <= '0'; write_threshold_reg <= '0'; enable_data_taking <= '0'; enable_int_strobe <= '0'; disable_int_strobe <= '0'; load_bias_dac <= '0'; load_trim_dac <= '0'; load_cc_counter <= '0'; chip_address <= (others => '0'); elsif (CLK='1' and CLK'event) then if (execute='1') then chip_address <= data(21 downto 16); elsif (send_triggers='1') then chip_address <= "111111"; else chip_address <= chip_address; end if; if (execute='1') then set_trigger_delay <= command_demux(0); load_num_triggers <= command_demux(1); send_soft_reset <= command_demux(2); send_bc_reset <= command_demux(3); write_config_reg <= command_demux(4); reset_mask_reg_pointer <= command_demux(5); write_mask_reg <= command_demux(6); send_mask_reg <= command_demux(7); write_strobe_delay_reg <= command_demux(8); write_threshold_reg <= command_demux(9); enable_data_taking <= command_demux(10); enable_int_strobe <= command_demux(11); disable_int_strobe <= command_demux(12); load_bias_dac <= command_demux(13); load_trim_dac <= command_demux(14); load_cc_counter <= command_demux(15); else set_trigger_delay <= '0'; load_num_triggers <= '0'; send_soft_reset <= '0'; send_bc_reset <= '0'; write_config_reg <= '0'; reset_mask_reg_pointer <= '0'; write_mask_reg <= '0'; send_mask_reg <= '0'; write_strobe_delay_reg <= '0'; write_threshold_reg <= '0'; enable_data_taking <= '0'; enable_int_strobe <= '0'; disable_int_strobe <= '0'; load_bias_dac <= '0'; load_trim_dac <= '0'; load_cc_counter <= '0'; end if; end if; end process latch_command; out_stream : process (CLK,RST) begin -- out_stream if (RST='1') then bitstream <= '0'; elsif (CLK'event and CLK='1') then bitstream <= soft_reset(6) or bc_reset(6) or enable_data_taking_reg(26) or config_reg(42) or strobe_delay_reg(42) or threshold_reg(42) or bias_dac_reg(42) or trim_dac_reg(42) or mask_reg(154) or issue_pulse_reg(26) or trig_signal_reg(2); end if; end process out_stream; busy_counter_process : process (CLK,RST) begin -- busy_counter_process if (RST='1') then busy_counter <= ("00000000"); start_signal <= '0'; elsif (CLK'event and CLK='1') then if (write_strobe_delay_reg='1' or send_soft_reset='1' or send_bc_reset='1' or write_config_reg='1' or write_threshold_reg='1' or enable_data_taking='1' or load_bias_dac='1' or load_trim_dac='1') then busy_counter <= "00110000"; start_signal <= '1'; elsif (send_mask_reg='1') then busy_counter <= "10100000"; start_signal <= '1'; else busy_counter <= busy_counter-1; start_signal <= '0'; end if; end if; end process busy_counter_process; busy_signal : process (CLK,RST) begin -- busy_signal if (RST='1') then busy_int <= '0'; elsif (CLK'event and CLK='1') then if (start_signal='1') then busy_int <= '1'; elsif (std_logic_vector(busy_counter)="00000001") then busy_int <= '0'; else busy_int <= busy_int; end if; end if; end process busy_signal; sm_busy_process : process (CLK,RST) begin -- sm_busy_process if (RST='1') then sm_busy <= '0'; elsif (CLK'event and CLK='1') then if (state=idle_st) then sm_busy <= '0'; else sm_busy <= '1'; end if; end if; end process sm_busy_process; num_triggers_process : process (CLK,RST) begin -- num_triggers_process if (RST='1') then num_triggers <= (others => '0'); elsif (CLK'event and CLK='1') then if (load_num_triggers='1') then num_triggers <= data(15 downto 0); else num_triggers <= num_triggers; end if; end if; end process num_triggers_process; trigger_delay_reg_process : process (CLK,RST) begin -- trigger_delay_reg_process if (RST='1') then trigger_delay <= (others => '0'); elsif (CLK'event and CLK='1') then if (set_trigger_delay='1') then trigger_delay <= data(15 downto 0); else trigger_delay <= trigger_delay; end if; end if; end process trigger_delay_reg_process; soft_reset_process : process (CLK,RST) begin -- soft_reset_process if (RST='1') then soft_reset <= (others => '0'); elsif (CLK'event and CLK='1') then if (send_soft_reset='1') then soft_reset <= "1010100"; else soft_reset(0) <= '0'; soft_reset(6 downto 1) <= soft_reset(5 downto 0); end if; end if; end process soft_reset_process; bc_reset_process : process (CLK,RST) begin -- bc_reset_process if (RST='1') then bc_reset <= (others => '0'); elsif (CLK'event and CLK='1') then if (send_bc_reset='1') then bc_reset <= "1010010"; else bc_reset(0) <= '0'; bc_reset(6 downto 1) <= bc_reset(5 downto 0); end if; end if; end process bc_reset_process; config_reg_process : process (CLK,RST) begin -- config_reg_process if (RST='1') then config_reg <= (others => '0'); elsif (CLK'event and CLK='1') then if (write_config_reg='1') then config_reg(42 downto 36) <= "1010111"; config_reg(35 downto 28) <= "00011100"; config_reg(27 downto 22) <= chip_address; config_reg(21 downto 16) <= "000000"; config_reg(15 downto 0) <= data(15 downto 0); else config_reg(0) <= '0'; config_reg(42 downto 1) <= config_reg(41 downto 0); end if; end if; end process config_reg_process; mask_reg_pointer_process : process (CLK,RST) begin -- mask_reg_pointer_process if (RST='1') then mask_reg_pointer <= "00"; elsif (CLK'event and CLK='1') then if (reset_mask_reg_pointer='1') then mask_reg_pointer <= "00"; elsif (write_mask_reg='1') then mask_reg_pointer <= mask_reg_pointer+1; else mask_reg_pointer <= mask_reg_pointer; end if; end if; end process mask_reg_pointer_process; mask_process : process (CLK,RST) begin -- mask_process if (RST='1') then mask_0 <= (others => '0'); mask_1 <= (others => '0'); mask_2 <= (others => '0'); mask_3 <= (others => '0'); elsif (CLK'event and CLK='1') then if (write_mask_reg='1') then if (std_logic_vector(mask_reg_pointer)="00") then mask_0 <= data(31 downto 0); mask_1 <= mask_1; mask_2 <= mask_2; mask_3 <= mask_3; elsif (std_logic_vector(mask_reg_pointer)="01") then mask_0 <= mask_0; mask_1 <= data(31 downto 0); mask_2 <= mask_2; mask_3 <= mask_3; elsif (std_logic_vector(mask_reg_pointer)="10") then mask_0 <= mask_0; mask_1 <= mask_1; mask_2 <= data(31 downto 0); mask_3 <= mask_3; else mask_0 <= mask_0; mask_1 <= mask_1; mask_2 <= mask_2; mask_3 <= data(31 downto 0); end if; else mask_0 <= mask_0; mask_1 <= mask_1; mask_2 <= mask_2; mask_3 <= mask_3; end if; end if; end process mask_process; send_mask : process (CLK,RST) begin -- send_mask if (RST='1') then mask_reg <= (others => '0'); elsif (CLK'event and CLK='1') then if (send_mask_reg='1') then mask_reg(154 downto 148) <= "1010111"; mask_reg(147 downto 140) <= "10001100"; mask_reg(139 downto 134) <= chip_address; mask_reg(133 downto 128) <= "001000"; mask_reg(127 downto 96) <= mask_3; mask_reg(95 downto 64) <= mask_2; mask_reg(63 downto 32) <= mask_1; mask_reg(31 downto 0) <= mask_0; else mask_reg(0) <= '0'; mask_reg(154 downto 1) <= mask_reg(153 downto 0); end if; end if; end process send_mask; strobe_delay_process : process (CLK,RST) begin -- strobe_delay_process if (RST='1') then strobe_delay_reg <= (others => '0'); elsif (CLK'event and CLK='1') then if (write_strobe_delay_reg='1') then strobe_delay_reg(42 downto 36) <= "1010111"; strobe_delay_reg(35 downto 28) <= "00011100"; strobe_delay_reg(27 downto 22) <= chip_address; strobe_delay_reg(21 downto 16) <= "010000"; strobe_delay_reg(15 downto 0) <= data(15 downto 0); else strobe_delay_reg(0) <= '0'; strobe_delay_reg(42 downto 1) <= strobe_delay_reg(41 downto 0); end if; end if; end process strobe_delay_process; threshold_process : process (CLK,RST) begin -- threshold_process if (RST='1') then threshold_reg <= (others => '0'); elsif (CLK'event and CLK='1') then if (write_threshold_reg='1') then threshold_reg(42 downto 36) <= "1010111"; threshold_reg(35 downto 28) <= "00011100"; threshold_reg(27 downto 22) <= chip_address; threshold_reg(21 downto 16) <= "011000"; threshold_reg(15 downto 0) <= data(15 downto 0); else threshold_reg(0) <= '0'; threshold_reg(42 downto 1) <= threshold_reg(41 downto 0); end if; end if; end process threshold_process; enable_datataking_process : process (CLK,RST) begin -- enable_datataking_process if (RST='1') then enable_data_taking_reg <= (others => '0'); elsif (CLK'event and CLK='1') then if (enable_data_taking='1') then enable_data_taking_reg(5 downto 0) <= "101000"; enable_data_taking_reg(11 downto 6) <= chip_address; enable_data_taking_reg(19 downto 12) <= "00001100"; enable_data_taking_reg(26 downto 20) <= "1010111"; else enable_data_taking_reg(0) <= '0'; enable_data_taking_reg(26 downto 1) <= enable_data_taking_reg(25 downto 0); end if; end if; end process enable_datataking_process; internal_strobe_process : process (CLK,RST) begin -- internal_strobe_process if (RST='1') then internal_strobe_enabled <= '0'; elsif (CLK'event and CLK='1') then if (enable_int_strobe='1') then internal_strobe_enabled <= '1'; elsif (disable_int_strobe='1') then internal_strobe_enabled <= '0'; else internal_strobe_enabled <= internal_strobe_enabled; end if; end if; end process internal_strobe_process; bias_dac_process : process (CLK,RST) begin -- bias_dac_process if (RST='1') then bias_dac_reg <= (others => '0'); elsif (CLK'event and CLK='1') then if (load_bias_dac='1') then bias_dac_reg(42 downto 36) <= "1010111"; bias_dac_reg(35 downto 28) <= "00011100"; bias_dac_reg(27 downto 22) <= chip_address; bias_dac_reg(21 downto 16) <= "111000"; bias_dac_reg(15 downto 0) <= data(15 downto 0); else bias_dac_reg(0) <= '0'; bias_dac_reg(42 downto 1) <= bias_dac_reg(41 downto 0); end if; end if; end process bias_dac_process; trim_dac_process : process (CLK,RST) begin -- trim_dac_process if (RST='1') then trim_dac_reg <= (others => '0'); elsif (CLK'event and CLK='1') then if (load_trim_dac='1') then trim_dac_reg(42 downto 36) <= "1010111"; trim_dac_reg(35 downto 28) <= "00011100"; trim_dac_reg(27 downto 22) <= chip_address; trim_dac_reg(21 downto 16) <= "000100"; trim_dac_reg(15 downto 0) <= data(15 downto 0); else trim_dac_reg(0) <= '0'; trim_dac_reg(42 downto 1) <= trim_dac_reg(41 downto 0); end if; end if; end process trim_dac_process; end structure; LIBRARY ieee; USE ieee.std_logic_1164.ALL; entity test_connector is port( CLK : in std_logic; LAST_COMMAND : in std_logic_vector(4 downto 0); RST : in std_logic; RUNNING : in std_logic; VALID_VME_ACCESS : in std_logic; t0 : in std_logic; t1 : in std_logic; t2 : in std_logic; t3 : in std_logic; t4 : in std_logic; t5 : in std_logic; t6 : in std_logic; t7 : in std_logic; t8 : in std_logic; t9 : in std_logic; LED : out std_logic_vector(8 downto 0); TC : out std_logic_vector(19 downto 0) ); end test_connector; architecture structure of test_connector is signal valid_vme_access_int : std_logic; begin LED(7 downto 5) <= "000"; TC(0) <= t0; TC(1) <= t1; TC(2) <= t2; TC(3) <= t3; TC(4) <= t4; TC(5) <= t5; TC(6) <= t6; TC(7) <= t7; TC(8) <= t8; TC(9) <= t9; TC(19 downto 10) <= "0000000000"; sync : process (CLK,RST) begin -- sync if (RST='1') then LED <= (others => '0'); valid_vme_access_int <= '0'; elsif (CLK'event and CLK='1') then LED(4 downto 0) <= LAST_COMMAND; if (VALID_VME_ACCESS='1') then valid_vme_access_int <= not valid_vme_access_int; else valid_vme_access_int <= valid_vme_access_int; end if; LED(8) <= valid_vme_access_int; end if; end process sync; end structure; LIBRARY ieee; USE ieee.std_logic_1164.ALL; entity module_controller is port( BUSY : in std_logic; CLK : in std_logic; MEM_DATAH_MB0_I : in std_logic_vector(8 downto 0); MEM_DATAH_MB1_I : in std_logic_vector(8 downto 0); MEM_DATAL_MB0_I : in std_logic_vector(8 downto 0); MEM_DATAL_MB1_I : in std_logic_vector(8 downto 0); RESYNC_FIFO_DATA : in std_logic_vector(17 downto 0); RST : in std_logic; SIM_MEM_CNT_RST : in std_logic; SIM_MEM_WRITE : in std_logic; START : in std_logic; TV_MEM_CNT_RST : in std_logic; TV_MEM_WRITE : in std_logic; VME_DATA : in std_logic_vector(17 downto 0); BS_MB0 : out std_logic_vector(2 downto 0); BS_MB1 : out std_logic_vector(2 downto 0); DIFFERENCE_FOUND : out std_logic; G_MB0 : out std_logic_vector(1 downto 0); G_MB1 : out std_logic_vector(1 downto 0); LOAD : out std_logic; MEM0_TRISTATE : out std_logic_vector(3 downto 0); MEM1_TRISTATE : out std_logic_vector(3 downto 0); MEM_ADDR_MB0 : out std_logic_vector(18 downto 0); MEM_ADDR_MB1 : out std_logic_vector(18 downto 0); MEM_DATAH_MB0_O : out std_logic_vector(8 downto 0); MEM_DATAH_MB1_O : out std_logic_vector(8 downto 0); MEM_DATAL_MB0_O : out std_logic_vector(8 downto 0); MEM_DATAL_MB1_O : out std_logic_vector(8 downto 0); OUTFIFO_DATA : out std_logic_vector(17 downto 0); READ_FROM_FIFO : out std_logic; RECEIVE_DATA : out std_logic; RESET_FIFO : out std_logic; RESYNC_FIFO_RST : out std_logic; RUNNING : out std_logic; SEND_FIFO : out std_logic; SW_MB0 : out std_logic; SW_MB1 : out std_logic ); end module_controller; architecture structure of module_controller is signal busy_int : std_logic_vector(3 downto 0); begin -- for now to avoid error msg BS_MB0 <= "001"; BS_MB1 <= "001"; avoid_errors : process (CLK,RST) begin -- avoid_errors if (RST='1') then busy_int<= (others => '0'); MEM_ADDR_MB0 <= (others => '0'); MEM_ADDR_MB1 <= (others => '0'); G_MB0 <= (others => '1'); G_MB1 <= (others => '1'); MEM0_TRISTATE <= (others => '0'); MEM1_TRISTATE <= (others => '0'); SW_MB0 <= '0'; SW_MB1 <= '0'; elsif (CLK'event and CLK='1') then busy_int(0) <= BUSY; busy_int(1) <= BUSY; busy_int(2) <= BUSY; busy_int(3) <= BUSY; if (busy_int(0)='1') then MEM_ADDR_MB0 <= (others => '0'); else MEM_ADDR_MB0 <= (others => '1'); end if; if (busy_int(1)='1') then MEM_ADDR_MB1 <= (others => '0'); else MEM_ADDR_MB1 <= (others => '1'); end if; if (busy_int(2)='1') then MEM0_TRISTATE <= (others => '0'); MEM1_TRISTATE <= (others => '0'); else MEM0_TRISTATE <= (others => '1'); MEM1_TRISTATE <= (others => '1'); end if; if (busy_int(3)='1') then G_MB0 <= (others => '1'); G_MB1 <= (others => '1'); SW_MB0 <= '0'; SW_MB1 <= '0'; else G_MB0 <= (others => '0'); G_MB1 <= (others => '0'); SW_MB0 <= '1'; SW_MB1 <= '1'; end if; end if; end process avoid_errors; end structure; LIBRARY ieee; USE ieee.std_logic_1164.ALL; use ieee.std_logic_arith.all; entity serialtoparallel is port( clk : in std_logic; rst : in std_logic; serial_data : in std_logic; bc : out std_logic_vector(7 downto 0); channel : out std_logic_vector(6 downto 0); chip : out std_logic_vector(3 downto 0); l1t : out std_logic_vector(3 downto 0); write : out std_logic ); end serialtoparallel; architecture structure of serialtoparallel is -- TYPE DECLARATIONS type StateType is (wait_for_header,save_header,wait_a,wait_for_trailer,whats_up,save_first_hit,wait_b,no_hit,wait_c,save_error,wait_d,adjacent_hit_dec,save_hit,wait_e,save_config_data,wait_f,wait_to_save_head); -- SIGNAL DECLARATIONS signal state : StateType; signal data,data_copy : std_logic_vector(30 downto 0);--SR for ABC(D) data signal cnt1 : unsigned(4 downto 0); -- counter for wait's in fsm signal do_save_header : std_logic; signal do_save_first_hit : std_logic; signal local_channel : unsigned(6 downto 0); signal header_detect,wrong_header_detect : std_logic; signal save_header_now,trailer_detect : std_logic; signal save_first_hit_detect,no_hit_detect : std_logic; signal save_config_data_detect : std_logic; signal save_error_detect : std_logic; constant header : std_logic_vector(4 downto 0) := "10111"; constant wrong_header : std_logic_vector(4 downto 0) := "01111"; constant trailer : std_logic_vector(15 downto 0) := "0000000000000001"; begin channel <= std_logic_vector(local_channel); fsm : process (rst,clk) begin -- fsm if (rst='1') then state <= wait_for_header; do_save_header <= '0'; do_save_first_hit <= '0'; elsif (clk'event and clk='1') then do_save_first_hit <= '0'; do_save_header <= '0'; case state is when wait_for_header => if ((header_detect='1') or (wrong_header_detect='1')) then if (save_header_now='1') then state <= save_header; do_save_header <= '1'; else state <= wait_to_save_head; end if; else state <= wait_for_header; end if; when save_header => state <= wait_a; when wait_to_save_head => state <= save_header; do_save_header <= '1'; when wait_a => if (std_logic_vector(cnt1)="10000") then state <= whats_up; else state <= wait_a; end if; when whats_up => if (trailer_detect='1') then state <= wait_for_header; -- this is the trailer, start over else if (save_first_hit_detect='1') then state <= save_first_hit; -- at least one hit found in first chip do_save_first_hit <= '1'; elsif (no_hit_detect='1') then state <= no_hit; -- no hit found elsif (save_config_data_detect='1') then state <= save_config_data; -- chip sent config data elsif (save_error_detect='1') then state <= save_error; -- chip gave error msg else state <= wait_for_trailer; -- should never get here. Just in when.. end if; end if; when no_hit => state <= wait_c; when wait_c => state <= whats_up; when save_error => state <= wait_d; when wait_d => if ((std_logic_vector(cnt1)="01001") and (trailer_detect='1')) then state <= wait_for_header; elsif (std_logic_vector(cnt1)="01001") then state <= whats_up; else state <= wait_d; end if; when save_config_data => state <= wait_f; when wait_f => if ((std_logic_vector(cnt1)="11001") and (trailer_detect='1')) then state <= wait_for_header; elsif (std_logic_vector(cnt1)="11001") then state <= whats_up; else state <= wait_f; end if; when save_first_hit => state <= wait_b; when wait_b => if (std_logic_vector(cnt1)="01110") then state <= adjacent_hit_dec; else state <= wait_b; end if; when adjacent_hit_dec => if (trailer_detect='1') then state <= wait_for_header; -- this is the trailer, start over elsif (data(0)='1') then state <= save_hit; -- another hit in the same data packet elsif (save_first_hit_detect='1') then state <= save_first_hit; -- a new data packet do_save_first_hit <= '1'; elsif (save_error_detect='1') then state <= save_error; -- error message elsif (no_hit_detect='1') then state <= no_hit; -- no hit data packet else state <= wait_for_trailer; -- should never get here. Just in case.. end if; when save_hit => state <= wait_e; when wait_e => if (std_logic_vector(cnt1)="00001") then state <= adjacent_hit_dec; else state <= wait_e; end if; when wait_for_trailer => if (trailer_detect='1') then state <= wait_for_header; else state <= wait_for_trailer; -- to recover from errors end if; when others => state <= wait_for_header; end case; end if; end process fsm; additional_ff : process (CLK,RST) begin -- additional flip flops to reduce the number of passes through -- combinational logic gates for each clock cycle (for a few -- critical signals) if (rst='1') then header_detect <= '0'; wrong_header_detect <= '0'; save_header_now <= '0'; trailer_detect <= '0'; save_first_hit_detect <= '0'; no_hit_detect <= '0'; save_config_data_detect <= '0'; save_error_detect <= '0'; elsif (clk'event and clk='1') then if (data(3 downto 1)="000") then save_error_detect <= '1'; else save_error_detect <= '0'; end if; if (data_copy(3 downto 1)="000" and data_copy(10 downto 8)="111") then save_config_data_detect <= '1'; else save_config_data_detect <= '0'; end if; if (data(3 downto 1)="100") then no_hit_detect <= '1'; else no_hit_detect <= '0'; end if; if (data_copy(2 downto 1)= "10") then save_first_hit_detect <= '1'; else save_first_hit_detect <= '0'; end if; if (data(16 downto 1)=trailer) then trailer_detect <= '1'; else trailer_detect <= '0'; end if; if (data_copy(20 downto 19)="01") then save_header_now <= '1'; else save_header_now <= '0'; end if; if (data(5 downto 1)=header) then header_detect <= '1'; else header_detect <= '0'; end if; if (data_copy(5 downto 1)=wrong_header) then wrong_header_detect <= '1'; else wrong_header_detect <= '0'; end if; end if; end process additional_ff; clk_it : process (rst,clk) begin -- clk_it if (rst='1') then data <= (others => '0'); data_copy <= (others => '0'); cnt1 <= "00000"; write <= '0'; bc <= (others => '0'); local_channel <= (others => '0'); chip <= (others => '0'); elsif (clk'event and clk='1') then -- fix bug on board by inverting input signals data(30) <= not serial_data; data_copy(30) <= not serial_data; data(29 downto 0) <= data(30 downto 1); data_copy(29 downto 0) <= data_copy(30 downto 1); if ((state=save_header) or (state=save_first_hit) or (state=no_hit) or (state=save_error) or (state=save_config_data) or (state=save_hit)) then cnt1<= "00000"; else cnt1 <= cnt1+'1'; end if; if (do_save_header='1') then l1t(0)<=data(8); l1t(1)<=data(7); l1t(2)<=data(6); l1t(3)<=data(5); bc(0)<=data(16); bc(1)<=data(15); bc(2)<=data(14); bc(3)<=data(13); bc(4)<=data(12); bc(5)<=data(11); bc(6)<=data(10); bc(7)<=data(9); end if; if (do_save_first_hit='1') then chip(3)<=data(1);chip(2)<=data(2);chip(1)<=data(3);chip(0)<=data(4); local_channel(6)<=data(5);local_channel(5)<=data(6);local_channel(4)<=data(7); local_channel(3)<=data(8);local_channel(2)<=data(9);local_channel(1)<=data(10); local_channel(0)<=data(11); end if; if (state=save_hit) then local_channel<=local_channel+1; end if; if (state=save_hit or state=save_first_hit) then write <= '1'; else write <= '0'; end if; end if; end process clk_it; end structure; -- libraries library ieee; USE ieee.std_logic_1164.ALL; use ieee.std_logic_arith.all; -- i/o ports ------------------------------------------------------ entity fifo_controller is port( CLK : in std_logic; READ : in std_logic; CLEAR : in std_logic; -- NEEDS TO BE IMPLEMENTED RST : in std_logic; WRITE : in std_logic; WREN : out std_logic; EMPTY : out std_logic; FULL : out std_logic; READ_ADDR : out std_logic_vector(4 downto 0); WRITE_ADDR : out std_logic_vector(4 downto 0) ); end fifo_controller; -- architecture --------------------------------------------------- architecture structure of fifo_controller is signal full_int,empty_int,write_int : std_logic; signal read_cnt,write_cnt,flag_cnt : unsigned(4 downto 0); begin FULL <= full_int; EMPTY <= empty_int; READ_ADDR <= std_logic_vector(read_cnt); WRITE_ADDR <= std_logic_vector(write_cnt); WREN <= write_int and not full_int; read_counter : process (clk,rst) begin -- read_counter if (rst='1') then read_cnt <= (others => '0'); elsif (clk'event and clk='1') then if (READ='1' and empty_int='0') then read_cnt <= read_cnt+1; end if; end if; end process read_counter; write_counter : process (clk,rst) begin -- write_counter if (rst='1') then write_cnt <= (others => '0'); elsif (clk'event and clk='1') then if (write_int='1' and full_int='0') then write_cnt <= write_cnt+1; end if; end if; end process write_counter; flag_circuitry : process (clk,rst) begin -- flag_circuitry if (rst='1') then full_int <= '0'; empty_int <= '1'; flag_cnt <= (others => '0'); elsif (clk'event and clk='1') then if (write_int='1' and full_int='0' and READ='0') then flag_cnt <= flag_cnt+1; elsif (write_int='0' and READ='1' and empty_int='0') then flag_cnt <= flag_cnt-1; else flag_cnt <= flag_cnt; end if; if (std_logic_vector(flag_cnt)="00000") then empty_int <= '1'; else empty_int <= '0'; end if; if (std_logic_vector(flag_cnt)="11111") then full_int <= '1'; else full_int <= '0'; end if; end if; end process flag_circuitry; write_ff : process (clk,rst) begin -- write_ff if (rst='1') then write_int <= '0'; elsif (clk'event and clk='1') then if (WRITE='1') then write_int <= '1'; else write_int <= '0'; end if; end if; end process write_ff; end structure; LIBRARY ieee; USE ieee.std_logic_1164.ALL; use ieee.std_logic_arith.all; entity histo_circ is port( BASE_ADDRESS : in std_logic_vector(7 downto 0); LOAD_BASE_ADDRESS : in std_logic; CLK : in std_logic; BUSY : out std_logic; MEMORY_CLEAR : in std_logic; MEM_DATAH_MB2_I : in std_logic_vector(8 downto 0); MEM_DATAH_MB3_I : in std_logic_vector(8 downto 0); MEM_DATAL_MB2_I : in std_logic_vector(8 downto 0); MEM_DATAL_MB3_I : in std_logic_vector(8 downto 0); READ : in std_logic; RST : in std_logic; START_HISTOGRAMMING : in std_logic; STOP_HISTOGRAMMING : in std_logic; channel_A : in std_logic_vector(6 downto 0); channel_B : in std_logic_vector(6 downto 0); chip_A : in std_logic_vector(3 downto 0); chip_B : in std_logic_vector(3 downto 0); empty_A : in std_logic; empty_B : in std_logic; full_A : in std_logic; full_B : in std_logic; read_A : out std_logic; read_B : out std_logic; clear_fifo_A : out std_logic; clear_fifo_B : out std_logic; BS_MB2 : out std_logic_vector(2 downto 0); BS_MB3 : out std_logic_vector(2 downto 0); G_MB2 : out std_logic_vector(1 downto 0); G_MB3 : out std_logic_vector(1 downto 0); MEM2_TRISTATE : out std_logic_vector(3 downto 0); MEM3_TRISTATE : out std_logic_vector(3 downto 0); MEM_ADDR_MB2 : out std_logic_vector(18 downto 0); MEM_ADDR_MB3 : out std_logic_vector(18 downto 0); MEM_DATAH_MB2_O : out std_logic_vector(8 downto 0); MEM_DATAH_MB3_O : out std_logic_vector(8 downto 0); MEM_DATAL_MB2_O : out std_logic_vector(8 downto 0); MEM_DATAL_MB3_O : out std_logic_vector(8 downto 0); SW_MB2 : out std_logic; SW_MB3 : out std_logic; VME_READ_DATA : out std_logic_vector(31 downto 0) ); end histo_circ; architecture structure of histo_circ is type StateType is (idle_st,rst_fifo_st,histo_st,wait_0,wait_1,wait_2,wait_for_end_st,clear_mem); type StateType2 is (idle,fifo_empty_dec,h00,h0,h1,h2,h3,h4,h5); signal sm_state, sm_state_par : StateType; signal state_A,state_B : StateType2; signal start_histogramming_int : std_logic; signal stop_histogramming_int : std_logic; signal do_histogramming : std_logic; signal A_busy,B_busy,main_busy : std_logic; signal mem_addr_A_cnt,mem_addr_B_cnt,clear_cnt : unsigned(18 downto 0); signal mem_data_A_in_int : std_logic_vector(15 downto 0); signal mem_data_A_out_int : unsigned(15 downto 0); signal mem_data_B_in_int : std_logic_vector(15 downto 0); signal mem_data_B_out_int : unsigned(15 downto 0); signal write_A,write_A_d1 : std_logic; signal write_B,write_B_d1 : std_logic; signal clear_done,clear_mem_cnt_en : std_logic; signal trist_A_0,trist_A_1,trist_A_2 : std_logic; signal g_A0,g_A1,g_A2,g_A3 : std_logic; signal trist_B_0,trist_B_1,trist_B_2 : std_logic; signal g_B0,g_B1,g_B2,g_B3 : std_logic; begin MEM_ADDR_MB2 <= std_logic_vector(mem_addr_A_cnt); MEM_ADDR_MB3 <= std_logic_vector(mem_addr_B_cnt); BS_MB2 <= "001"; BS_MB3 <= "001"; histo_mem_A_controller : process (CLK,RST) begin if (RST='1') then MEM2_TRISTATE <= (others => '1'); G_MB2 <= (others => '1'); SW_MB2 <= '1'; elsif (CLK'event and CLK='1') then if (g_A0='1' or g_A1='1' or g_A2='1' or g_A3='1') then G_MB2 <= "11"; else G_MB2(0) <= std_logic(mem_addr_A_cnt(18)); G_MB2(1) <= not std_logic(mem_addr_A_cnt(18)); end if; if (trist_A_2='0' or sm_state_par=clear_mem) then MEM2_TRISTATE <= (others => '0'); else MEM2_TRISTATE <= (others => '1'); end if; if (write_A_d1='1' or sm_state=clear_mem) then SW_MB2 <= '0'; else SW_MB2 <= '1'; end if; end if; end process histo_mem_A_controller; histo_mem_B_controller : process (CLK,RST) begin if (RST='1') then MEM3_TRISTATE <= (others => '1'); G_MB3 <= (others => '1'); SW_MB3 <= '1'; elsif (CLK'event and CLK='1') then if (g_B0='1' or g_B1='1' or g_B2='1' or g_B3='1') then G_MB3 <= "11"; else G_MB3(0) <= std_logic(mem_addr_B_cnt(18)); G_MB3(1) <= not std_logic(mem_addr_B_cnt(18)); end if; if (trist_B_2='0' or sm_state_par=clear_mem) then MEM3_TRISTATE <= (others => '0'); else MEM3_TRISTATE <= (others => '1'); end if; if (write_B_d1='1' or sm_state=clear_mem) then SW_MB3 <= '0'; else SW_MB3 <= '1'; end if; end if; end process histo_mem_B_controller; adder : process (CLK,RST) begin -- adder if (RST='1') then mem_data_A_out_int <= (others => '0'); mem_data_B_out_int <= (others => '0'); elsif (CLK'event and CLK='1') then if (sm_state=clear_mem) then mem_data_A_out_int <= (others => '0'); mem_data_B_out_int <= (others => '0'); --for testing: mem_data_A_out_int(15 downto 8) <= "00000000"; -- mem_data_B_out_int(15 downto 8) <= "00000000"; -- mem_data_A_out_int(7 downto 0) <= mem_addr_A_cnt(7 downto 0); -- mem_data_B_out_int(7 downto 0) <= mem_addr_A_cnt(7 downto 0); else mem_data_A_out_int <= unsigned(mem_data_A_in_int) +1; mem_data_B_out_int <= unsigned(mem_data_B_in_int) +1; end if; end if; end process adder; addr_cnt_A_proc : process (CLK,RST) begin -- addr_cnt_A_proc if (RST='1') then mem_addr_A_cnt <= (others => '0'); elsif (CLK'event and CLK='1') then if (READ='1' or clear_mem_cnt_en='1') then mem_addr_A_cnt <= mem_addr_A_cnt + 1; elsif (LOAD_BASE_ADDRESS='1') then mem_addr_A_cnt(18 downto 11) <= unsigned(BASE_ADDRESS); mem_addr_A_cnt(10 downto 0) <= "00000000000"; elsif (state_A=h1) then mem_addr_A_cnt(18 downto 11) <= mem_addr_A_cnt(18 downto 11); mem_addr_A_cnt(10 downto 7) <= unsigned(chip_A); mem_addr_A_cnt(6 downto 0) <= unsigned(channel_A); else mem_addr_A_cnt <= mem_addr_A_cnt; end if; end if; end process addr_cnt_A_proc; addr_cnt_B_proc : process (CLK,RST) begin -- addr_cnt_B_proc if (RST='1') then mem_addr_B_cnt <= (others => '0'); elsif (CLK'event and CLK='1') then if (READ='1' or clear_mem_cnt_en='1') then mem_addr_B_cnt <= mem_addr_B_cnt + 1; elsif (LOAD_BASE_ADDRESS='1') then mem_addr_B_cnt(18 downto 11) <= unsigned(BASE_ADDRESS); mem_addr_B_cnt(10 downto 0) <= "00000000000"; elsif (state_B=h1) then mem_addr_B_cnt(18 downto 11) <= mem_addr_B_cnt(18 downto 11); mem_addr_B_cnt(10 downto 7) <= unsigned(chip_B); mem_addr_B_cnt(6 downto 0) <= unsigned(channel_B); else mem_addr_B_cnt <= mem_addr_B_cnt; end if; end if; end process addr_cnt_B_proc; clear_counter_process : process (CLK,RST) begin -- clear_counter_process if (RST='1') then clear_cnt <= (others => '0'); elsif (CLK'event and CLK='1') then if (clear_mem_cnt_en='1') then clear_cnt <= clear_cnt + 1; elsif (LOAD_BASE_ADDRESS='1') then clear_cnt <= (others => '0'); else clear_cnt <= clear_cnt; end if; end if; end process clear_counter_process; io_flipflops : process (CLK,RST) begin -- io_flipflops if (RST='1') then BUSY <= '0'; start_histogramming_int <= '0'; stop_histogramming_int <= '0'; clear_fifo_A <= '0'; clear_fifo_B <= '0'; VME_READ_DATA <= (others => '0'); mem_data_A_in_int <= (others => '0'); mem_data_B_in_int <= (others => '0'); MEM_DATAH_MB2_O <= (others => '0'); MEM_DATAL_MB2_O <= (others => '0'); MEM_DATAH_MB3_O <= (others => '0'); MEM_DATAL_MB3_O <= (others => '0'); elsif (CLK'event and CLK='1') then if (sm_state=idle_st) then BUSY <= '0'; else BUSY <= '1'; end if; mem_data_A_in_int(15 downto 8) <= MEM_DATAH_MB2_I(7 downto 0); mem_data_A_in_int(7 downto 0) <= MEM_DATAL_MB2_I(7 downto 0); mem_data_B_in_int(15 downto 8) <= MEM_DATAH_MB3_I(7 downto 0); mem_data_B_in_int(7 downto 0) <= MEM_DATAL_MB3_I(7 downto 0); MEM_DATAH_MB2_O(7 downto 0) <= std_logic_vector(mem_data_A_out_int(15 downto 8)); MEM_DATAL_MB2_O(7 downto 0) <= std_logic_vector(mem_data_A_out_int(7 downto 0)); MEM_DATAH_MB3_O(7 downto 0) <= std_logic_vector(mem_data_B_out_int(15 downto 8)); MEM_DATAL_MB3_O(7 downto 0) <= std_logic_vector(mem_data_B_out_int(7 downto 0)); VME_READ_DATA(31 downto 16) <= mem_data_A_in_int; VME_READ_DATA(15 downto 0) <= mem_data_B_in_int; start_histogramming_int <= START_HISTOGRAMMING; stop_histogramming_int <= STOP_HISTOGRAMMING; if (start_histogramming_int='1') then clear_fifo_A <= '1'; clear_fifo_B <= '1'; else clear_fifo_A <= '0'; clear_fifo_B <= '0'; end if; end if; end process io_flipflops; internal_flipflops : process (CLK,RST) begin -- internal_flipflops if (RST='1') then sm_state_par <= idle_st; do_histogramming <= '0'; A_busy <= '0'; B_busy <= '0'; main_busy <= '0'; write_A <= '0'; write_A_d1 <= '0'; write_B <= '0'; write_B_d1 <= '0'; clear_mem_cnt_en <= '0'; read_A <= '0'; read_B <= '0'; trist_A_0 <= '1';trist_A_1 <= '1';trist_A_2 <= '1'; g_A0 <= '0';g_A1 <= '0';g_A2 <= '0';g_A3 <= '0'; trist_B_0 <= '1';trist_B_1 <= '1';trist_B_2 <= '1'; g_B0 <= '0';g_B1 <= '0';g_B2 <= '0';g_B3 <= '0'; elsif (CLK'event and CLK='1') then if (state_B=h4) then g_B0 <= '1'; else g_B0 <= '0'; end if; g_B1 <= g_B0;g_B2 <= g_B1;g_B3 <= g_B2; if (state_B=h4 or state_B=h5) then trist_B_0 <= '0'; else trist_B_0 <= '1'; end if; trist_B_1 <= trist_B_0;trist_B_2 <= trist_B_1; if (state_A=h4) then g_A0 <= '1'; else g_A0 <= '0'; end if; g_A1 <= g_A0;g_A2 <= g_A1;g_A3 <= g_A2; if (state_A=h4 or state_A=h5) then trist_A_0 <= '0'; else trist_A_0 <= '1'; end if; trist_A_1 <= trist_A_0;trist_A_2 <= trist_A_1; if (state_A=h1) then read_A <= '1'; else read_A <= '0'; end if; if (state_B=h1) then read_B <= '1'; else read_B <= '0'; end if; if (sm_state_par=clear_mem) then clear_mem_cnt_en <= '1'; else clear_mem_cnt_en <= '0'; end if; if (state_A=h5) then write_A <= '1'; else write_A <= '0'; end if; if (state_B=h5) then write_B <= '1'; else write_B <= '0'; end if; write_A_d1 <= write_A; write_B_d1 <= write_B; sm_state_par <= sm_state; if (sm_state_par=idle_st) then main_busy <= '0'; else main_busy <= '1'; end if; if (sm_state_par=histo_st) then do_histogramming <= '1'; else do_histogramming <= '0'; end if; if (state_A=idle) then A_busy <= '0'; else A_busy <= '1'; end if; if (state_B=idle) then B_busy <= '0'; else B_busy <= '1'; end if; end if; end process internal_flipflops; clear_process : process (CLK,RST) begin -- clear_process if (RST='1') then clear_done <= '0'; elsif (CLK='1' and CLK'event) then if (sm_state=idle_st) then clear_done <= '0'; elsif (std_logic_vector( -- true clear_cnt(18 downto 0))="1111111111111111101") then -- sim: clear_cnt(18 downto 0))="0000000000011111101") then clear_done <= '1'; else clear_done <= clear_done; end if; end if; end process clear_process; sm1 : process (CLK,RST) begin -- sm1 if (RST='1') then sm_state <= idle_st; elsif (CLK'event and CLK='1') then case sm_state is when idle_st => if (start_histogramming_int='1') then sm_state <= rst_fifo_st; elsif (MEMORY_CLEAR='1') then sm_state <= clear_mem; else sm_state <= idle_st; end if; when clear_mem => if (clear_done='1') then sm_state <= idle_st; else sm_state <= clear_mem; end if; when rst_fifo_st => sm_state <= wait_0; when wait_0 => sm_state <= wait_1; when wait_1 => sm_state <= wait_2; when wait_2 => sm_state <= histo_st; when histo_st => if (stop_histogramming_int='1') then sm_state <= wait_for_end_st; else sm_state <= histo_st; end if; when wait_for_end_st => if (A_busy='1' or B_busy='1') then sm_state <= wait_for_end_st; else sm_state <= idle_st; end if; when others => sm_state <= idle_st; end case; end if; end process sm1; sm_A : process (CLK,RST) begin -- sm_A if (RST='1') then state_A <= idle; elsif (CLK'event and CLK='1') then case state_A is when idle => if (do_histogramming='1') then state_A <= fifo_empty_dec; else state_A <= idle; end if; when fifo_empty_dec => if (do_histogramming='0') then state_A <= idle; elsif (empty_A='1') then state_A <= fifo_empty_dec; else state_A <= h00; end if; when h00 => state_A <= h0; when h0 => state_A <= h1; when h1 => state_A <= h2; when h2 => state_A <= h3; when h3 => state_A <= h4; when h4 => state_A <= h5; when h5 => if (empty_A='0') then state_A <= h00; else state_A <= fifo_empty_dec; end if; end case; end if; end process sm_A; sm_B : process (CLK,RST) begin -- sm_B if (RST='1') then state_B <= idle; elsif (CLK'event and CLK='1') then case state_B is when idle => if (do_histogramming='1') then state_B <= fifo_empty_dec; else state_B <= idle; end if; when fifo_empty_dec => if (do_histogramming='0') then state_B <= idle; elsif (empty_B='1') then state_B <= fifo_empty_dec; else state_B <= h00; end if; when h00 => state_B <= h0; when h0 => state_B <= h1; when h1 => state_B <= h2; when h2 => state_B <= h3; when h3 => state_B <= h4; when h4 => state_B <= h5; when h5 => if (empty_B='0') then state_B <= h00; else state_B <= fifo_empty_dec; end if; end case; end if; end process sm_B; end structure;