The LHC poses unprecedented challenges in designing tracking detector electronics that combine low noise, single-bunch time resolution and low power consumption with high radiation resistance. Beyond these electronic requirements, the sheer scale and the inaccessibility of the silicon tracking systems require high reliability and economical fabrication and testing, so avoiding undue complexity is an important goal in these designs.
The binary readout records only the presence and beam crossing interval of a hit. The position resolution is given directly by the strip pitch of the silicon detector and does not rely on analog amplitude interpolation. Efficiency and occupancy are determined by the signal/noise ratio and the threshold matching.
The analog front-end chain consists of a preamplifier, shaper and comparator. Comparator hits are stored in a time-sliced binary buffer, clocked at the beam crossing frequency. Upon receipt of a trigger signal, the hit pattern in the appropriate time slice is used to provide a sparsified readout. This represents the simplest form of a sparse readout system and allows substantial simplifications in the practical implementation, since
In these implementations, the readout chain is split into two ICs: an analog
chip (preamplifier, shaper, comparator) utilizing bipolar transistor
technology, and a digital chip (data buffer with time stamp and readout)
fabricated in CMOS. Both types of ICs have been fabricated with
radiation-hard processes and tested. Suitable radiation-hard processes for
both the bipolar transistor and CMOS chips are available from multiple
foundries and performance has been demonstrated with various processes.